{"slug": "ibm-z-and-linuxone-dual-isa-processor-and-ai-acceleration-at-hot-chips-2026", "title": "IBM Z and LinuxONE Dual-ISA Processor and AI Acceleration at Hot Chips 2026", "summary": "IBM detailed its future IBM Z and LinuxONE dual-ISA processor and second-generation AI inference accelerator at Hot Chips 2026, with the chip carrying 11 IBM Z cores at 5.7+ GHz on a 2nm process, each natively executing both z/Architecture and AArch64. IBM Distinguished Engineer Christian Zoellin presented the design, which includes 36MB private L2 caches, a 432MB virtual L3, 3.5GB virtual L4, and full hardware AArch64 support with 2,792 implemented instructions, targeting 99.999999% availability. The move aims to bring the Arm ecosystem to IBM Z mainframes, which handle about 70% of the world's transaction volume.", "body_md": "IBM took the Hot Chips 2026 stage to detail its future IBM Z and LinuxONE processors and the AI inference acceleration chipset that sits beside it. IBM Distinguished Engineer Christian Zoellin is walking through a dual-ISA core that natively runs both z/Architecture and Arm AArch64, and then covered a second-generation on-chip AI accelerator aimed at larger enterprise inference workloads. We previously got to see [The IBM z17 Mainframe Brings AI with Telum II and Spyre](https://www.servethehome.com/the-ibm-z17-mainframe-brings-ai-with-telum-ii-and-spyre/) and [The New IBM z17 Telum II Processor Module Cut Open Down to Silicon](https://www.servethehome.com/the-new-ibm-z17-telum-ii-processor-module-cut-open-down-to-silicon/) in cool pieces.\n\nThis is being done live from the session, so please excuse typos.\n\n## IBM Z and LinuxONE Dual-ISA Processor and AI Acceleration at Hot Chips 2026\n\nIBM opened with the historical context for Z, tracing a lineage that runs from out-of-order execution and 64-bit Linux through pervasive encryption, post-quantum security, and now AI. This arc frames Z as the reliability base onto which IBM is attaching more modern capabilities. Something like 70% of the world’s transaction volume goes over IBM Z mainframes. It says that by bring in the Arm ecosystem, it is bringing in a new class of applications to IBM Z mainframes.\n\nNow comes the core of the announcement, a mainframe-grade, dual-ISA processor. This chip carries 11 IBM Z cores at 5.7+ GHz on a 2nm process, and each core can natively execute both z/Architecture and AArch64. IBM pairs those cores with large 36MB private L2 caches joined into a virtual L3/L4, plus a dedicated on-chip DPU for I/O acceleration and dedicated blocks for AI, compression, cryptography, and sort. This is also a SMT=2 design and has a 432MB Virtual-L3 and 3.5GB virtual L4 cache. That was not on the slide we got, but they showed those specs live.\n\nA key choice here is that IBM implemented AArch64 in full hardware rather than through translation. This design uses a little-endian Arm implementation alongside big-endian z/Architecture, with AArch64 v9.3, SVE and SVE2 support, and 2,792 implemented AArch64 instructions. IBM also claims Arm SystemReady compliance, which matters for how much off-the-shelf Arm software this core can absorb. This is absolutely crazy technology. Arm software sees a native Arm processor. Arm runs unmodified, out-of-the-box, and onto a standard Arm platform. IBM said the 2792 AArch64 instructions are more than twice the Z instructions. IBM made a funny quip about “reduced” in RISC.\n\nBranch prediction shows how much of the existing Z core design IBM was able to reuse for AArch64. Automation consumes Arm’s XML architecture descriptions to feed decode, while dispatch and issue repurpose register rename for the GR16-31 range. IBM calls out new control for SVE, new dataflows for FP16, Bfloat16, and crypto, and even non-obvious CISC reuse such as memory copy and clear. I am sitting here still in awe of what IBM is doing here, this is not Z+Arm cores, this is Z and Arm in one core.\n\nOn the software side, IBM exposes the Z accelerators as platform devices to Linux on Arm. Crypto, GZIP compression, and the on-chip AI unit surface as Linux devices with comparable latency to native Z instructions, while the Z ISA can still expose them as instructions for s390x workloads.\n\nReliability carries over to this design with a 99.999999% availability target. IBM cites error checking across arrays, dataflows, and control, transparent recovery from transient faults, core sparing for persistent faults, and concurrent repair, plus RAIM memory protection. If you saw our video on the Z17, the engineering that IBM did to make its systems reliable is very different from general purpose cloud servers. Actually, NVIDIA has been doing some similar things like replacing many cables with PCB to increase reliability of its systems.\n\nRather than forcing a single ecosystem, IBM positions the cores to coexist through Linux KVM and OpenShift Virtualization. This figure maps s390x Linux and ARM64 Linux alongside IBM z/OS, with logical partitions sharing the same processor. A thread can run either s390x or Arm software and the switch takes nanoseconds.\n\nTogether, that coexistence is the pitch for getting the best of both software ecosystems, letting Z customers keep mainframe code while tapping the wide Arm software base. That is why IBM did not just integrate existing Arm cores.\n\nIBM’s second-generation AI inference accelerator targets larger enterprise workloads. This chip packs 16 active AI cores plus one redundant core, with FP4 and MXFP4 datatypes that IBM says can deliver up to 4x TOPS. Amazing, this is AI with redundancy. It adds 96GB of HBM3e running up to about 4TB/s, roughly 20x the memory bandwidth of the current generation, and uses PCIe Gen6 as a low-latency peer-to-peer interface.\n\nOn the security and resilience side, IBM positions this part for mission-critical AI with confidential computing that protects data and models at rest, in transit, and in use, including quantum-safe cryptography. Secure boot and on-chip cryptography combine with a firmware stack tuned for availability and serviceability and tight operational integration with IBM Z.\n\nIBM packs a lot into this roadmap, from a native dual-ISA core that merges the mainframe reliability story with the Arm ecosystem to a serious enterprise AI inference part for larger workloads.\n\n## Final Words\n\nI have sat through almost a decade of Hot Chips presentations. This is one of the presentations I am almost in awe of. IBM’s dual-ISA bet is a bid to keep the mainframe relevant as Arm software and AI workloads reshape the data center, rather than treating Z as a closed platform. The fact that they had this idea, and implemented it the hard way I would have had no concept of two years ago. After doing the Z17 launch content, I know the answer is just that IBM has engineers that take on crazy hard problems. Still, it is awesome. This is a 2nm core with native AArch64 execution and the second-generation AI accelerator take on two pressures at once, software ecosystem breadth and AI inference density. How much of the surrounding Arm software stack runs unmodified on the core will be worth watching.", "url": "https://wpnews.pro/news/ibm-z-and-linuxone-dual-isa-processor-and-ai-acceleration-at-hot-chips-2026", "canonical_source": "https://www.servethehome.com/ibm-z-and-linuxone-dual-isa-processor-and-ai-acceleration-at-hot-chips-2026/", "published_at": "2026-08-24 16:47:50+00:00", "updated_at": "2026-08-24 17:13:54.455084+00:00", "lang": "en", "topics": ["artificial-intelligence", "ai-chips"], "entities": ["IBM", "Christian Zoellin", "IBM Z", "LinuxONE", "Arm", "z/Architecture", "AArch64", "Hot Chips 2026"], "alternates": {"html": "https://wpnews.pro/news/ibm-z-and-linuxone-dual-isa-processor-and-ai-acceleration-at-hot-chips-2026", "markdown": "https://wpnews.pro/news/ibm-z-and-linuxone-dual-isa-processor-and-ai-acceleration-at-hot-chips-2026.md", "text": "https://wpnews.pro/news/ibm-z-and-linuxone-dual-isa-processor-and-ai-acceleration-at-hot-chips-2026.txt", "jsonld": "https://wpnews.pro/news/ibm-z-and-linuxone-dual-isa-processor-and-ai-acceleration-at-hot-chips-2026.jsonld"}}