I Let an AI Agent Design My Raspberry Pi CM4 Board — 486 Checks Later, Here's the Scoreboard

A developer has spent two days running an AI coding agent (Codex) through an inspect-and-fix loop to design a Mini-ITX I/O carrier board for the Raspberry Pi CM4, driving KiCad entirely from the command line via kicad-cli and custom scripts. The agent runs ERC and DRC, compares schematic and PCB nets, and performs DC analysis on the power rails; the electrical rule check is now clean and the 5V rail passed 486 analysis conditions, though routing has only begun and the power design remains problematic. The current layout is still marked "UNROUTED ENGINEERING DRAFT / DO NOT FABRICATE.

TL;DR: For two days, an AI coding agent Codex has been designing a Mini-ITX I/O board for the Raspberry Pi CM4 by driving KiCad from the command line in an inspect → fix loop. ERC is clean, the 5V rail passed 486 analysis conditions, routing has started — and the power design is fighting back. This is build log 1. I'm building a carrier board for the Raspberry Pi Compute Module 4. Or, more accurately: I'm watching one get built. The designer is an AI agent working through kicad-cli and scripted checks — running ERC/DRC, comparing schematic and PCB nets, doing DC analysis on the power rails, fixing what the checks flag, and re-running. My job is reading its inspection reports and looking at renders. It feels less like prompting a chatbot and more like supervising a very fast, very literal junior engineer who never sleeps and documents everything. If you know the CM4, you see the problem immediately: the module exposes one PCIe Gen2 x1 lane, and DisplayPort isn't native to it. Cramming this into Mini-ITX, with ATX soft-power handling on top, is exactly the kind of dense, constraint-heavy problem I wanted to throw at the loop. Everything goes through the CLI and scripts, roughly like this: kicad-cli sch erc board.kicad sch electrical rule check kicad-cli pcb drc board.kicad pcb design rule check + custom scripts: net consistency, power DC analysis across tolerances No GUI, no mouse. Just checks, fixes, and re-checks — hundreds of iterations. The moment that made me start this log is a clearance check in the power section. On the front copper, a signal trace D4 TX N has to pass the projection of the back-side MOSFET's drain pad — Q901, sitting next to the R900 current shunt. The drain is a high-current power net, so the loop projects the back-side pad onto the front view and routes the signal around it, checking clearance point by point. Unglamorous, invisible work. Also the work that decides whether a board works at all. The silkscreen on the current layout literally reads "UNROUTED ENGINEERING DRAFT / DO NOT FABRICATE". Accurate. If you've designed CM4 carrier boards: Genuinely collecting answers — the loop and I are still deciding, and I'd rather learn from your scars than earn my own. Part 2 when routing finishes or when the startup analysis finally completes instead of timing out — whichever comes first .