The 48V Imperative in Modern Data Centers
At the recent OCP Global Summit, NVIDIA officially released a white paper outlining the next-phase development blueprint for AI factory power infrastructure. The new architecture innovatively shifts from traditional 415 VAC or 480 VAC to an end-to-end 800 VDC bus, eliminating redundant intermediate AC-DC conversion stages and delivering high-voltage DC power directly to computing nodes. This approach not only significantly reduces transmission losses but also saves up to 26% of space compared to traditional multi-stage conversion solutions.
Within this hierarchical power architecture, the 48V supply rail has become critical to improving system efficiency. High-voltage bus architectures such as 800 VDC solve long-distance power transmission at the rack level, but the final stretch from 48 V down to the processor core remains the hardest segment. As AI processors push into the kilowatt class, their core voltages stay near 0.8 V to 1.1 V while load currents climb toward the kiloampere range, with microsecond-scale load transients. Point-of-Load (PoL) DC/DC converters are therefore necessary to deliver the low operating voltage directly on-site, right at the processor. Otherwise, the I²R losses across long low-voltage distribution paths would become unacceptable. The PoL load in this context includes general-purpose and application-specific processors, GPUs, FPGAs, and ASICs.
Two-Stage vs. Single-Stage Conversion
View All The Traditional Two-Stage Approach
In the conventional 48V architecture, the mainstream solution uses a two-stage conversion topology. First, an Intermediate Bus Converter (IBC) steps down 48 V to a 12 V intermediate bus voltage. Then, a multi-phase buck PoL converter converts 12V down to the ultra-low voltage required by chip cores such as MCUs, FPGAs, or ASICs. The first stage can achieve a peak efficiency of around 96% (up to 97% or higher in some designs), and the second-stage multi-phase buck converter reaches roughly 92% peak efficiency on its own. Because the end-to-end efficiency is the product of the two stages, the result is approximately 88% before system-level losses. When further accounting for distribution losses, parasitic impedance, and other real-world factors across the full power path, the two-stage system typically delivers only about 86% end-to-end efficiency.
The two-stage approach remains the industry mainstream, largely because the supply chain is mature and the architecture is straightforward to scale by adding phases or modules. However, it carries inherent drawbacks. The final-stage inductor must carry the full DC load current, which makes the magnetic components difficult to shrink, and the hard-switched buck limits how far the switching frequency can be pushed. The architecture also requires two independent power conversion modules and corresponding magnetic components, increasing the overall volume and material cost. The longer power path introduces greater parasitic impedance, which degrades dynamic response performance, and the 12 V intermediate bus means high distribution currents that generate significant copper losses on the board.
The Single-Stage Direct Conversion Advantage
In contrast, the single-stage direct conversion architecture converts the 48V input directly to the target low voltage in one step. By eliminating the intermediate conversion stage, the typical overall efficiency rises to 90–92% at the peak operating point, representing a 2 to 4% gain over the best two-stage solutions. Bringing 48V closer to the load also reduces distribution copper losses dramatically, since the current, and thus the I²R loss, drops in proportion to the square of the voltage ratio. Industry research shows that even a modest 1 to 2% improvement in PoL efficiency yields substantial energy savings at data-center scale.
In terms of physical layout, single-stage conversion can reduce the active power-conversion area by up to roughly 75% and cut component count by around 40%, by eliminating the intermediate bus circuit and leveraging higher switching frequencies. The shorter power path also reduces loop inductance, thereby optimizing load transient response performance.
The HP1800: A Practical Path to Single-Stage 48 V to Ultra-Low Voltage
To bridge the gap between single-stage topology and practical implementation, Hynetek offers the HP1800 complementary PWM phase-doubler. Specifically designed for high-density, high-efficiency DC-DC power supplies, this chip expands a single tri-state PWM input into four outputs, forming two complementary phases interleaved at 180°. It allows the second-stage multi-phase controller from a traditional two-stage solution to directly drive a single-stage half-bridge current-doubler rectifier with 48 V input, without requiring any additional PWM control signals, and is compatible with standard DrMOS or discrete driver solutions.
HP1800 Chip Features
VCC maximum supply voltage: 7 VSignalextension: From a single PWM input signal, outputs four PWM signals with two complementary phases interleaved at 180°Switching frequency range: 200 kHz to 2 MHzTri-state input: PWM_IN supports tri-state signal input; high-impedance state is used to stop PWM outputProgrammable dead time: Initial PWM dead-time configuration is programmableOperating temperature range:-40°C to 125°C
Typical Application Block Diagram
The HP1800 drives a multi-phase interleaved half-bridge current-doubler rectifier converter (HBCD). This converter steps down a typical 48 V input to ultra-low voltage through single-stage power conversion, significantly improving efficiency compared to the two-stage approach. The PWM_IN and EN signals are controlled by an external traditional multi-phase controller, while the PWM1 to PWM4 outputs simultaneously drive the half-bridge driver HP3010 (120 V/3 A, DFN2x2-8L) and the dual-channel low-side driver HP3000 (30 V/5 A, DFN2x2-8L).
The initial dead-time between complementary signal pairs (PWM1/PWM2 and PWM3/PWM4) can be independently configured through resistor R1 at the PWM1 terminal and resistor R4 at the PWM4 terminal. This allows fine-tuning of the dead-time to match the specific switching characteristics of the power devices used.
Highlight 1: Complementary PWM Phase-Doubling Output
The HP1800 expands a single tri-state PWM input signal into four PWM output signals with two complementary phases interleaved at 180°. This greatly facilitates main power topologies that require multi-phase complementary PWM drive, reducing the design demands on the main controller’s PWM output channels.
Additionally, through pull-down resistors on PWM1 and PWM4, the dead-time for PWM1/PWM2 and PWM3/PWM4 can be independently initialized and configured, allowing flexible adjustment according to the actual system requirements.
Highlight 2: Comprehensive Anti-Disturbance Mechanism
Since the four complementary PWM output signals are controlled solely by a single PWM input signal, any disturbance or abnormal timing on the PWM input can pose a serious threat to output stability. In severe cases, complementary signals may shoot through, damaging power devices.
Shoot-Through Risk: If complementary PWM signals overlap due to input disturbance, both high-side and low-side switches can conduct simultaneously, creating a low-impedance path from input to ground that can destroy power devices instantly.
The HP1800 addresses this by optimizing the control logic for the PWM input signal entering or exiting the tri-state (high-impedance) condition, as well as the output complementary signal timing. This effectively handles external sudden abnormal interference.
Highlight 3: Enabling Multi-Phase HBCD with Legacy Controllers Using the HP1800
A primary challenge in adapting a conventional multi-phase controller to drive an interleaved half-bridge current-doubler rectifier is the inadequacy of available PWM output channels. This requirement typically exceeds the output capacity of most standard controllers without the addition of external logic circuitry. The HP1800 effectively resolves this issue. As shown in Figure 8, it takes just one tri-state PWM input from the existing multi-phase controller and expands it into four complementary outputs arranged as two phases interleaved at 180°. This allows the controller to drive the entire two-phase half-bridge current-doubler converter using only a single PWM pin, eliminating the need for a dedicated controller with many PWM channels.
Conclusion
Compared to the traditional two-stage power solution, the single-stage topology enabled by the HP1800 delivers higher efficiency, simpler design, and a fresh approach to computing power delivery. By expanding a single PWM input into four complementary outputs with programmable dead-time and robust anti-disturbance protection, the HP1800 allows designers to migrate from two-stage to single-stage 48 V to ultra-low voltage conversion without requiring additional PWM control signals, thereby significantly lowering the barrier to adoption.
As data centers (AIDC) continue to scale toward AI workloads with ever-increasing power demands, single-stage PoL conversion will play a critical role in reducing energy waste, CO2 emissions, and system cost. The HP1800 positions itself as a key enabler in this industry-wide transition, offering a practical migration path from two-stage to single-stage architecture without the overhead of new PWM control infrastructure.