Josh Millar lead an article just out in GETMOBILE on our work from last year on benchmarking micro-NPUs to help make sense of the growing number of dedicated, ultra-low-power 'neural network accelerators'. There are lots of hidden embedded NPUs in modern low-cost chips, ranging from ESP32-based boards over to ARM ones. All of these have quite a variety of tradeoffs, from the operations supported (which affects which models can be run on them) to the amount of memory and CPU power.
If you'd like a shorter, more accessible summary of that paper, then [head over](https://dl.acm.org/doi/pdf/10.1145/3833428.3833430) to read our article. Feedback is most welcome!
While the hardware landscape hasn't changed hugely since last year's article, the software one has. I'm now finding that using coding agents to write low-level embedded code is far far faster than before. Modern harnesses are pretty good at figuring out the various quirks of each cross-compilation and embedded environment...
source & further reading
anil.recoil.org — original article
.plan-26-30: Bananas ripen, models open, and OxCaml releases
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.plan-26-26: Gelato, geospatial, and players of games