From AI-Assisted EDA to AI-Mediated Engineering

Agentic AI accounted for roughly 28% of the 2026 Design Automation Conference (DAC) agenda, with 54 dedicated sessions and AI submissions rising from under 300 in 2023 to approximately 700, according to an account of the event. More than half of 32 new exhibitors came from AI companies, and Synopsys executive director Frank Schirrmeister said many agentic founders are "AI people who found EDA, not EDA people who found AI." The shift marks a move from AI-assisted EDA to AI-mediated engineering, with Nvidia, AMD, and Microsoft acting as kingmakers supplying agentic stacks and acceleration platforms, while trust, specification quality, tool latency, and the EU AI Act remain open problems.

Eighteen months ago, AI in EDA was still largely an EDA story: established tool teams and design groups dabbling with copilots, scripts, and point optimizers bolted onto 40-year-old flows. However, this year’s 2026 Design Automation Conference DAC showed a different industry. Agentic AI became the organizing theme of the program, accounting for roughly 28% of the conference agenda. There were 54 dedicated sessions, AI submissions increased from under 300 in 2023 to approximately 700, and more than half of 32 new exhibitors came from AI companies. More important than the percentages was the change in who was driving progress. AI people found EDA, and they were no longer guests in the hallway. They were setting the technical agenda. Two related developments ran in parallel: AI for creating chips, and chips for AI. Production verification triage moved from days to minutes. Model Context Protocol MCP emerged as a practical agent-to-tool interface. A structural split appeared between startups that wrap today’s engines and frontier labs that rebuild them. At the same time, the AI compute giants, Nvidia, AMD, Microsoft, and their peers, behaved less like EDA competitors and more like kingmakers: supplying the agentic stacks, acceleration platforms, and buyer demand on which both incumbents and startups now depend. This is not usefully described as a technology bubble. Earlier EDA breakthroughs depended on rare heuristic expertise. The present wave applies mathematics and compute at a scale no individual flow can replicate by hand. Trust, specification quality, tool latency, and regulation, including the EU AI Act, remain open engineering and compliance problems. View All https://www.eetimes.com/category/sponsored-content/ However, the direction of travel is clear: AI is no longer an add-on to EDA. It is becoming a new layer of the semiconductor engineering stack. DAC 2026 marked the move from AI-assisted EDA to AI-mediated engineering. This article is my perspective on how that is progressing, and why this is a genuine transition moment in the EDA industry. Sections in this article: From dabbling to driving: the eighteen-month arc from-dabbling-to-driving The week AI became the organizing theme the-week-AI Scale, content mix, and regional contribution scale-content-mix Agentic verification arrived in production agentic-verification Replace the engines, wrap them, and recognize the kingmakers replace-the-engines Impatient agents meet slow tools impatient-agents DIY EDA, MCP, and who owns the flow DIY-EDA Who verifies the verifier, “silent hallucination,” and the EU AI Act who-verifies EDA finding AI, and AI finding EDA EDA-finding-AI From dabbling to driving: the eighteen-month arc The useful way to read DAC 2026 is as the end of one phase and the start of another. In the earlier phase, progress was framed as EDA people experimenting with AI. The questions were incremental: can a large language model LLM draft a testbench, triage a log, or suggest a placement tweak? The expertise center of gravity remained inside classic EDA, such as Tcl flows, sign-off engines, Universal Verification Methodology UVM , and vendor roadmaps that treated AI as a feature. By mid-2026, the center of gravity had moved. Frank Schirrmeister, executive director for strategic programs and system solutions at Synopsys, noted that many agentic founders are “AI people who found EDA, not EDA people who found AI.” DAC 2026 made that observation visceral. The strongest technical sessions were often led by people whose primary craft was AI systems, reinforcement learning, agent harnesses, and model training, applied to semiconductor constraints they had taken seriously enough to rebuild, not merely decorate. The Veriest startup session, “The Autonomous Silicon Loop: How AI Is Transforming Chip Design, Verification, and Innovation,” brought that pattern together on one stage. It featured Anna Goldie Ricursive Intelligence , Ferdinando Frediani Move Silicon , Jonathan Birjiniuk Oboe , and William Salcedo par.tcl . All are first-time CEOs with frontier machine-learning expertise, attacking tool latency, deterministic inner loops, analog sign-off, and agent-ready timing rather than wrapping yesterday’s whys. ChipAgents and Bronco showed the same pattern on the agentic verification side. The distinction matters for adopters. Band-aid automation around existing flows still benefits from deep EDA expertise, and that approach has improved since DVCon earlier this year. Transformational progress more often requires deep AI expertise applied to semiconductor problems. DAC 2026 was the conference where that second group stopped looking like outsiders and started looking like the people rewriting the pace of the field. The week AI became the organizing theme For several years, AI for EDA occupied specialist sessions and carefully scoped demonstrations. At DAC 2026, it organized the conference. Nvidia’s keynote framed three phases—accelerating core EDA, introducing AI physics and surrogates, then moving to agentic engineering—and stated that the third phase had arrived in 2026. John Cooley’s Troublemakers panel presented claims from Cadence, Synopsys, and Siemens around Level 5 “virtual engineers.” Microsoft’s “Vibes to Silicon” tutorial drew more than 300 attendees and treated agents as a methodology: text plus tools plus harness, with a measurable definition of done as the hardest step. Schirrmeister’s preview borrowed the Society of Automotive Engineers SAE Level 1 to Level 5 automation ladder and insisted that “what level?” is only half a claim; the other half is the operational design domain, autonomy inside one cockpit versus autonomy across the flow. That remains the right booth discipline. Industry behavior during the week, however, treated agent orchestration as a default more strongly than any single automation level suggested. Claude Code, Cursor, and Codex were repeatedly named as common agentic harnesses. MCP emerged as the vertical interface from agents to tools. IBM published FastMCP practices; Nvidia shipped an Agent Toolkit; the three large EDA vendors committed to MCP interoperability. Survey data still indicated near-universal shallow adoption and single-digit broad deployment. Tool integration, not novelty, remained the practical blocker. Scale, content mix, and regional contribution The quantitative picture reinforces the qualitative one. The overall program expanded by roughly 25–26% year on year. The Research Track recorded 2,443 submissions, an all-time high and a 30.7% increase over the prior year, reviewed by a Technical Program Committee of 721 members. The Engineering Track reached 458 submissions, up from 356 in 2025 and 199 in 2022, with 162 committee members. Schirrmeister described it as the “user conference within the conference” and used it as evidence for DIY AI. Student programs, including Hack@DAC, Young Fellows, PhD Forum, and University Demo, remained a visible part of the week. The exhibit floor added 32 first-time exhibitors, with AI companies forming the majority. Content share by topic was equally concentrated. AI, machine learning, LLMs, and agentic methods accounted for approximately 29.8% of papers, panels, and presentations in the analyzed program mix. Physical design, implementation, and sign-off followed at 17.5%. Verification, validation, formal methods, and debug contributed 14.2%. Memory topics such as high-bandwidth memory HBM , Compute Express Link CXL , compute-in-memory, and related storage issues contributed 11.2%. In short, DAC 2026 was an AI-centered semiconductor conference where verification and physical implementation remained the strongest traditional engineering themes underneath that wave. Regional contribution to the research program was uneven. China’s lead was both large and broad, with approximately 300 research papers, or 55% of the research set in the available counts. That presence was not confined to AI papers. Chinese institutions were prominent across architecture, verification, memory, systems, and traditional EDA, contributing roughly 56% of AI papers, 56% of Design papers, 52% of EDA papers, and 68% of Systems papers. The U.S. held a smaller numerical share of approximately 82 research papers, or 16%, but with a more diversified portfolio including strength in quantum computing, security, system architecture, and work connecting algorithms to practical design flows. Talent, data, and compute for AI-mediated design were globally distributed, while the shape of contribution differed by region with scale and breadth in one case, portfolio diversity in the other. Two AI revolutions at once DAC 2026 was not only an agentic-EDA conference. It was simultaneously an AI-computing conference, an AI-hardware conference, and an AI-for-engineering conference. Part 3 of the pre-DAC series https://www.eetimes.com/dac-2026-what-does-it-actually-take-to-create-ai-chips/ published by EE Times was right on this point: Amid funding announcements for AI that designs chips, it is worth remembering what DAC means for the chips and systems that come out the other end. Agentic methods were prominent. However, accelerators, memory systems, inference optimization, and verification collectively represented a larger body of work than agent demos alone. AI appeared in two forms. The first was AI for designing and verifying chips, including agentic EDA, RTL, and assertion generation, verification planning, debug, physical design, timing closure, analog sizing, and tool orchestration. The second was designing hardware for AI, such as LLM inference, GPUs, and NPUs, edge AI, quantization, sparsity, compute-in-memory, HBM, chiplets, power delivery, and thermal design. Physics does not negotiate on either side of that pair. Flows that address only one will miss half of the adoption pressure. Agentic verification arrived in production Verification was the clearest domain in which agentic AI looked industrial rather than speculative. Cadence ChipStack reported verification closure cycles collapsing from weeks to a day, cited in production at Nvidia. Synopsys presented autonomous design verification DV agents. Siemens reported Questa debug agents delivering order-of-magnitude gains. IBM’s MCP-based triage on IBM Z delivered a 15–40% improvement in debug productivity. Bronco AI reported full-chip triage moving from three or four days to 15 minutes, including emergent instrumentation behaviors that conventional waveform inspection would not normally pursue. Analog Devices, presenting with ChipAgents, framed success as “learning cycle velocity.” AMD stated that AI-generated IP is already taping out. Panel consensus was neither pure disruption nor pure collaboration. AI disrupts methodology while collaborating with simulation and formal analysis. A useful distinction emerged between reasoning over RTL and evidence-grounded loops. In the stronger pattern, AI proposes while physics, formal methods, or simulation decides. Stitch from ETH Zurich used formal counterexamples to guide LLM protocol repair. Move Silicon made the same point for analog sizing with Spectre sign-off. That pattern is closer to a deployable verification methodology than unconstrained generation, and it is the pattern toward which AI-native teams and incumbents alike are converging when tape-out risk is real. Replace the engines, wrap them, and recognize the kingmakers A structural split ran through the startup and frontier-lab presentations. One camp rebuilds computational engines often with deterministic, non-LLM inner loops so that design iteration economics change. Ricursive Intelligence, DeepPCB, Move Silicon, Cognichip, and par.tcl sit in this camp. The other camp orchestrates existing tools and human workflows. ChipAgents, Bronco, and related agentic layers focus on triage, debug, and multi-agent teams above today’s EDA stack. Schirrmeister sorted a related spectrum from companies that train their own silicon foundation models to companies that wrap frontier LLMs and differentiate on orchestration. Neither extreme is wrong; they are opposite bets on where value accrues. These theses should not be conflated. Wrapping legacy tools can deliver immediate return on investment ROI across fragmented flows. Replacing engines changes the computational substrate. A third reading of the market is at least as important: The AI technology giants are kingmakers, not EDA competitors. Nvidia, AMD, and Microsoft are not attempting to replace Synopsys, Cadence, or Siemens as owners of deterministic physics and sign-off. They supply compute anchors and agentic platforms. Nvidia, for example, provides Nemotron, NeMo, and the OpenShell stack, along with cloud discovery environments on which incumbent agent products and many startup demos now depend. They are also among the primary buyers. Hardware giants trust incumbent sign-off engines to deliver AI speedups without risking multi-million-dollar tape-out failures. AI cannot hallucinate physics; electromigration, timing, and thermal behavior still require deterministic engines that the Big Three have historically owned. That framing clarifies the niche for AI-first startups. Specialized disruptors can win in focused bottlenecks — analog block generation, RTL bug hunting, intent translation, impatient-agent infrastructure — without needing to rewrite the entire stack. The most successful of those companies may fortify incumbent platforms through partnerships or acquisitions rather than displace them. AI people are driving the pace of innovation, while AI compute platforms and incumbent physics engines jointly determine which companies can reach production silicon. Impatient agents meet slow tools Once agents became an assumed part of the flow, Amdahl’s law reasserted itself on the tool side. Agents reason in seconds and wait hours for simulation, emulation, timing, and waveform access. As agents accelerate manual tasks, raw tool runtime becomes the exposed bottleneck. Oboe demonstrated one debug iteration moving from roughly three hours to about two minutes by attacking FPGA emulation setup and waveform query latency. par.tcl made a related claim: static timing analysis STA on million-instance designs in tens of seconds. Qualcomm’s CTO keynote stated the buyer-side version of the same constraint. Reshaping one IP block in a floorplan with zero RTL change took a large team three months. The request to EDA was for foundation models with temporal, spatial, geometric, and textual reasoning; textual LLM reasoning alone is inadequate. Current AI in design verification DV was characterized as largely limited to testbench generation, while debug needs temporal reasoning. Tool speed is necessary infrastructure for agentic workflows. However, faster legacy loops are not, by themselves, a change in what can be designed or verified. This is exactly where AI-native infrastructure teams have found EDA: not as dabblers adding a chat window, but as engineers attacking the latency that makes agents starve. DIY EDA, MCP, and who owns the flow Large semiconductor companies building in-house agentic flows was treated as normal practice. Apple, Nvidia, Google, Samsung, and AMD appeared repeatedly in DIY discussions. Build-versus-buy settled on a hybrid consensus: Large companies own top-level orchestration and buy product-level agents; smaller companies buy more of the stack. Pure in-house construction can become a second product organization that was never planned, unless the organization already has the required expertise. Part 2 https://www.eetimes.com/dac-2026-users-are-not-waiting-diy-ai-is-now-in-vogue/ of EE Times’ pre-DAC series captured this wave well and pushed back on a caveat of mine: Hyperscaler DIY is “effective and myopic at the same time.” Both points are partly right. Samsung reinforcement-learning quality-of-service tuning, IBM agentic triage and MCP utility generation, and on-premises multi-agent pipelines did appear with deployment numbers rather than aspirations. That is progress. However, the deepest closed-loop learning, in which proprietary failure corpora, full design histories, and hyperscaler agent stacks still largely remain behind firewalls. The visible iceberg grew, but its underwater mass remained proprietary. Interoperability is a complementary issue. MCP as the agent-to-tool bus together with common harnesses will help determine whether the future AI engineering layer is portable across tools or captured inside individual vendor platforms. Accellera’s AI-EDA discussion emphasized data formats, Python-based application programming interfaces APIs , and knowledge bases for finetuning and retrieval-augmented generation RAG . For SoC developers and tool users, the near-term question is whether agent outputs can move between engines with shared evidence packages, or whether each vendor stack becomes a private silo. DIY at the hyperscalers is further evidence of the arc: Organizations with AI talent, EDA talent, and closed-loop data are not waiting for finished vendor solutions. Who verifies the verifier, “silent hallucination,” and the EU AI Act For roughly 40 years, mainstream EDA assumed deterministic, reproducible tools. Agents break that assumption. The “Who Verifies the Verifiers?” panel framed agentic output as something that must become measurable. AMD described agentic artefacts as alien objects requiring independent trust criteria, especially because AI-generated IP is already on a path to tape out. Cadence held that agents may operate up to sign-off, but sign-off remains protected, noting that a large share of EDA revenue historically comes from analysis tools checking construction tools. Independent checkers therefore become more valuable, not less. A useful term for the central failure mode, which I used in the Accellera panel, is “silent hallucination,” i.e., output that looks correct, is not correct, and cannot readily be identified as wrong. Related risks include agents writing their own waivers and correlated generator-and-checker failure from shared training distributions. Hardware cannot be patched like software after shipment. Verification remains an understanding problem, not only a generation problem. As generation cost falls, verification share of the overall engineering burden can rise. Governance and regulation now sit beside technical trust. On the Accellera AI-EDA panel, I made the point that a governance layer already exists: multiple IEEE standards relating to AI model transparency, autonomy, data privacy, and algorithmic bias; ISO guidance and certification processes; and the EU AI Act, effective from August 2026, bringing risk-tiered compliance into force. AI systems used in the design and testing of critical microelectronics, including chips designed for automotive, aerospace, or medical devices, can fall under high-risk classification. That implies conformity assessment, human-in-the-loop logging, and error-mitigation obligations before tools touch commercial data. For lean startups, compliance overhead, training-data provenance, export-control exposure, and IP liability are not side issues. They are part of the product. Incumbents absorb much of that cost through existing legal, security, and sign-off indemnity frameworks. Startups face a steeper barrier unless they wrap probabilistic agents in trusted deterministic engines and maintain cleanroom data custody. The practical implication is not that regulation freezes progress. It is that AI-mediated engineering must be designed for evidence, auditability, and sign-off from the start. Corporate AI style guides and prompting standards are the organizational counterparts. Without them, desktop chaos, with every engineer using whichever model they prefer, recreates the old problem of unmanaged scripts at AI scale. Specs, dilemmas, and tests Across panels, the same constraint recurred: An English PDF is not a sufficient specification for AI-mediated design, and a substantial fraction of intent often remains in the architect’s head. Machine-readable, AI-facing specification languages carried high thematic weight relative to their keyword volume. Most of the conference still accelerated artefacts that engineers already build: UVM generation, coverage closure, and mainstream triage. Spec-to-silicon probes remain early. They are also the clearest path beyond incremental automation. A useful framing for the industry pattern is the dilemma I posed in the April EDN article https://www.edn.com/what-is-the-eda-problem-worth-solving-with-ai/ and Schirrmeister covered in his pre-DAC articles . When every actor adopts AI rationally inside legacy processes, the collective outcome can still leave the shape of the tool chain unchanged. My associated test asks the sharper engineering question: does AI change what can be designed and verified, or does it only accelerate what was already done? Schirrmeister put both questions on the public itinerary for walking the floor. After DAC, both still sort the room. Much of what shipped fails the test and still delivers measurable ROI. Incremental agentic layers that compress triage cycles are valuable. They are not the same class of contribution as evidence-grounded loops, engine rebuilds, or search behaviors that surface previously unexamined failure modes. The 18-month talent shift improves the odds of passing the test. Regulation and kingmaker dynamics, however, still pull strongly toward wrapping trusted engines—the rational near-term path. EDA finding AI, and AI finding EDA DAC 2026 will be remembered as the point at which agentic AI entered semiconductor engineering as an organizing assumption rather than a side bet. The deeper story after the week is the reversal of agency. Eighteen months ago, EDA people were dabbling with AI. Now AI people have found EDA and are driving much of the visible progress while the Big Three retain the deterministic physics moat, and the AI compute giants act as kingmakers rather than EDA replacements. Verification provided the clearest near-term win. MCP and agent harnesses provided the interoperability layer. Engine rebuilders and agentic wrappers established two legitimate technical theses. Trust, specifications, tool latency, and the EU AI Act established that productivity without evidence packages and a compliance posture is incomplete. DIY hyperscaler stacks established that organizations with the best data have strong reasons to keep it private, while the tier below remains a substantial commercial market. The restrained reading of the current industry is that most of what shipped accelerates existing flows. The constructive reading is that the industry is building the talent mix, capital, early standards agenda, and self-critique required to go further. Agentic verification is becoming normal practice. Rebuilt deterministic engines are changing physical-design iteration economics. Evidence-grounded AI—proposed with models and deciding with physics and formal methods—is the more trustworthy deployment pattern, and it is also the pattern most compatible with high-risk regulatory regimes. Further work is needed on measurable trust for AI-generated IP, AI-facing specification languages, temporal and spatial reasoning for debug, independent evidence packages across tools, and practical compliance paths under the EU AI Act and related governance standards. If the industry can move from English PDFs and fragmented human workflows toward specification-driven, evidence-checked flows, AI-mediated engineering will change not only schedule but capabilities. DAC 2026 was not the end of that transition. It was the first major Design Automation Conference that behaved as if AI had already found EDA and EDA finally found AI. Also read: AI in EDA Is Real, It’s Now, and It’s on Show at DAC 2026 https://www.eetimes.com/ai-in-eda-is-real-its-now-and-its-on-show-at-dac-2026/ DAC 2026: Users Are Not Waiting; DIY AI Is Now in Vogue https://www.eetimes.com/dac-2026-users-are-not-waiting-diy-ai-is-now-in-vogue/ DAC 2026: What Does It Actually Take to Create AI Chips? https://www.eetimes.com/dac-2026-what-does-it-actually-take-to-create-ai-chips/ ADI Snaps Alif Semiconductor to Push AI into Physical Systems https://www.eetimes.com/adi-snaps-alif-semiconductor-to-push-ai-into-physical-systems/