arXiv:2609.30272v1 Announce Type: new Abstract: We present \textbf{ENAS}, a hardware-aware Neural Architecture Search (NAS) framework that combines a static feasibility check, a cell-based search space supporting standard, depthwise-separable, and bottleneck blocks with optional skip connections, and a three-stage hybrid search strategy (random $\rightarrow$ top-$K$ $\rightarrow$ mutation) with persistent cross-run caching. Unlike many existing NAS frameworks that rely on GPU acceleration, ENAS is designed to operate efficiently without requiring GPUs, making it suitable for resource-constrained development environments. We evaluate ENAS on two TinyML benchmarks, Visual Wake Words and Melanoma Cancer, across eight microcontrollers with memory footprints ranging from 20,KB to 1,MB SRAM and nine input image resolutions. Our experimental results show that ENAS achieves mean search-time speedups of $2.41{\times}$ and $1.70{\times}$ on the Visual Wake Words and Melanoma Cancer datasets, respectively, while maintaining competitive test accuracy compared with the recent NanoNAS framework. A measured resource analysis further shows that ENAS-selected models use substantially lower peak activation RAM, the binding constraint for microcontroller deployment at matched accuracy. Additionally, ENAS achieves $79.4%$ test accuracy on an STM32H743-based microcontroller, outperforming the greedy CPU-only baseline by $2.6$ percentage points. We release the ENAS framework as open-source at: https://github.com/EdgeIntelligenceLab/ENAS
ENAS: An Efficient Hardware-Aware Neural Architecture Search Framework for TinyML on Resource-Constrained Microcontrollers
Researchers released ENAS, an open-source hardware-aware Neural Architecture Search framework for TinyML that runs without GPUs, achieving mean search-time speedups of 2.41x on Visual Wake Words and 1.70x on Melanoma Cancer versus the NanoNAS framework. Evaluated across eight microcontrollers with 20 KB to 1 MB SRAM and nine input image resolutions, ENAS reached 79.4% test accuracy on an STM32H743-based microcontroller, 2.6 percentage points above the greedy CPU-only baseline, while using substantially lower peak activation RAM. The framework, posted to arXiv as 2609.30272v1, combines a static feasibility check, a cell-based search space with standard, depthwise-separable and bottleneck blocks, and a three-stage random-to-top-K-to-mutation search with persistent cross-run caching, and is available at github.com/EdgeIntelligenceLab/ENAS.
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