{"slug": "dnotitia-gets-its-vector-search-asic-back-from-fab-before-q4-tests", "title": "Dnotitia gets its vector-search ASIC back from fab before Q4 tests", "summary": "Dnotitia said on September 18 that first samples of its VDPU vector-search ASIC have returned from fabrication, with silicon characterization underway and ASIC-based systems planned for evaluation in the fourth quarter. The company reported that its four-card FPGA evaluation system delivered up to 5.77 times the vector-search throughput of a dual-socket CPU-only server, cut host CPU use during index construction by 92% and host memory use by 73% on a 4,096-dimensional multimodal workload, and is targeting as much as a 10x improvement over a CPU-based server once the ASIC ships. Latency, sustained query throughput, board power and system cost remain untested on the production silicon, so the FPGA results do not yet establish the economics of dedicated retrieval hardware.", "body_md": "# Dnotitia gets its vector-search ASIC back from fab before Q4 tests\n\n**Dnotitia reported a 5.77x FPGA gain, but silicon performance, power and cost remain untested ahead of planned evaluations.**\n\n        By [RuntimeWire Staff](https://runtimewire.com/author/runtimewire-staff)\n        · Published \n\nPrimary source: [PR Newswire](https://www.prnewswire.com/news-releases/dnotitia-brings-dedicated-vector-silicon-to-server-scale-at-ai-infra-summit-2026-302882731.html)\n\n## Why it matters\n\nDnotitia is testing whether AI retrieval deserves its own server processor. A successful ASIC could reduce CPU and GPU pressure, but FPGA results alone cannot establish the economics.\n\nMoo-Kyoung \"MK\" Chung's [Dnotitia](https://dnotitia.com/en/?ref=runtimewire) said in a [September 18th announcement](https://www.prnewswire.com/news-releases/dnotitia-brings-dedicated-vector-silicon-to-server-scale-at-ai-infra-summit-2026-302882731.html?ref=runtimewire) that the first samples of its VDPU vector-search chip have returned from fabrication. Dnotitia has started characterizing the silicon and plans to put ASIC-based systems into evaluation during the fourth quarter.\n\nThe milestone moves Chung's central bet beyond slides and FPGA prototypes. He founded Dnotitia in 2023 after serving as chief technology officer of SAPEON, SK Telecom's former AI chip subsidiary, according to [The Elec](https://thelec.net/news/articleView.html?idxno=4846&ref=runtimewire). Chung has built Dnotitia around the idea that AI systems need dedicated hardware for finding and moving data, rather than using every available CPU and GPU cycle for retrieval.\n\nCTO Se-Hyun Yang is leading the hardware side of that plan. Yang has spent more than 20 years designing processors and systems, including Samsung Electronics work on mobile CPUs and GPUs and AI-focused processors for data centers and supercomputers. He holds a doctorate in computer engineering from Carnegie Mellon University and electrical engineering degrees from KAIST, according to his [conference biography](https://www.design-reuse-embedded.com/ipsocdays/2025/korea/bios_virtual/bio.jsp?k=Se-Hyun%2BYang&ref=runtimewire).\n\nDnotitia showed a four-card VDPU server at the AI Infra Summit, held from September 15th through 17th in Santa Clara, California. The accelerator is intended to handle vector retrieval for retrieval-augmented generation and AI agents, leaving host processors and GPU memory available for application code and model execution.\n\n### The 5.77x result came from an FPGA\n\n[Dnotitia says](https://www.prnewswire.com/news-releases/dnotitia-brings-dedicated-vector-silicon-to-server-scale-at-ai-infra-summit-2026-302882731.html?ref=runtimewire) its four-card FPGA evaluation system produced up to 5.77 times the vector-search throughput of a dual-socket, CPU-only server running the same software stack. Dnotitia also reported equal or better recall, the quality measure used to track how many relevant nearest-neighbor results a search system retrieves.\n\nIn a 4,096-dimensional multimodal workload, Dnotitia says VDPU cut host CPU use during index construction by 92% and host memory use by 73%. The FPGA implementation supported FAISS, Milvus and hnswlib, with brute-force KNN, IVF, NSW and HNSW indexes.\n\nThose results do not measure the chip that came back from the fab. Dnotitia performed the tests on programmable FPGA hardware and supplied the benchmark methodology and results. The purchasing questions for an accelerator card remain open until the ASIC is tested: latency at useful recall levels, sustained query throughput, board power, system cost and performance across datasets that resemble production traffic.\n\nDnotitia is targeting as much as a 10x improvement over a CPU-based server once the ASIC is installed in a server. That figure is a design target. Q4 testing will determine whether the production silicon closes the gap between the 5.77x FPGA result and Dnotitia's target.\n\nAn earlier [The Elec report](https://thelec.net/news/articleView.html?idxno=4846&ref=runtimewire) said Dnotitia had selected Asicland to design a chip using TSMC's 12-nanometer process. Receiving samples gives Dnotitia working material to characterize, but it does not establish yield, production readiness or economics.\n\n### Chung is selling a dedicated memory layer for AI\n\nThe VDPU sits alongside [Seahorse](https://www.dnotitia.com/ko/products/seahorse/?ref=runtimewire), Dnotitia's vector database and AI storage platform. Owning both layers lets Dnotitia tune the database for its own accelerator and pitch a combined system instead of asking customers to assemble a database, search library and hardware stack separately.\n\nCompatibility matters because infrastructure buyers rarely replace established software solely to adopt a new chip. Dnotitia's support for FAISS, Milvus and hnswlib gives Yang's group a route into software environments that engineers already use. Dnotitia says it plans to add further libraries and databases when the ASIC enters evaluation.\n\nChung financed this hardware-software strategy with a roughly [$63M Series A](https://natlawreview.com/press-releases/dnotitia-closes-krw-90-billion-series-accelerate-ai-storage-expansion?ref=runtimewire) in April 2026. Elohim Partners led the round, with participation reported from Kiwoom Investment, Starting Line, Maple Investment Partners, Daesung Startup Investment, Shinhan Venture Investment, Ulmus Investment, Kolon Investment, HB Investment, Tony Investment, SJ Investment Partners and FuturePlay.\n\nThat capital buys the long development cycle required for custom silicon, database engineering and server integration. It also raises the standard for Dnotitia's next evidence. A chip company can attract early funding with architecture and simulation results. Infrastructure customers need repeatable measurements, support commitments and a supply path.\n\nDnotitia has been using industry events to recruit those partners. [RuntimeWire reported in August](https://runtimewire.com/article/dnotitia-fms-award-vdpu-ai-storage-partners) that Chung was turning Seahorse's Future of Memory and Storage award into conversations with storage and server vendors. The Santa Clara demonstration advanced that process from a card-level display to a four-card server architecture.\n\n### Retrieval already has several accelerators\n\nDnotitia is entering a market where vector retrieval can run on general-purpose CPUs, GPUs or storage-oriented systems. [NVIDIA cuVS](https://developer.nvidia.com/topics/ai/generative-ai/cuvs?ref=runtimewire) accelerates vector indexing and search on GPUs and integrates with FAISS, Milvus and other databases. [Kioxia's AiSAQ](https://americas.kioxia.com/en-us/business/resources/tech-brief/high-capacity-ssd-for-ai.html?ref=runtimewire) moves vector index structures onto high-capacity SSDs to reduce dependence on DRAM.\n\nChung's approach gives retrieval its own processor while preserving CPUs for applications and GPU high-bandwidth memory for model execution. The architecture will appeal only if the dedicated card saves enough CPU capacity, memory and power to justify another component in the server.\n\nThat makes the Q4 evaluation the consequential step. Dnotitia has a fabricated chip, an experienced processor architect and funding to pursue the retrieval bottleneck. The silicon now has to show that a dedicated vector processor earns its slot next to hardware customers already know how to buy and operate.", "url": "https://wpnews.pro/news/dnotitia-gets-its-vector-search-asic-back-from-fab-before-q4-tests", "canonical_source": "https://runtimewire.com/article/dnotitia-vdpu-vector-search-asic-back-from-fab", "published_at": "2026-09-18 15:46:41+00:00", "updated_at": "2026-09-18 15:57:08.582809+00:00", "lang": "en", "topics": ["ai-chips", "ai-infrastructure", "ai-agents", "ai-research"], "entities": ["Dnotitia", "Moo-Kyoung Chung", "Se-Hyun Yang", "SAPEON", "SK Telecom", "Samsung Electronics", "VDPU", "FAISS"], "alternates": {"html": "https://wpnews.pro/news/dnotitia-gets-its-vector-search-asic-back-from-fab-before-q4-tests", "markdown": "https://wpnews.pro/news/dnotitia-gets-its-vector-search-asic-back-from-fab-before-q4-tests.md", "text": "https://wpnews.pro/news/dnotitia-gets-its-vector-search-asic-back-from-fab-before-q4-tests.txt", "jsonld": "https://wpnews.pro/news/dnotitia-gets-its-vector-search-asic-back-from-fab-before-q4-tests.jsonld"}}