{"slug": "dancing-the-frantic-flash-fandango", "title": "Dancing the frantic flash fandango", "summary": "SK Hynix is developing 3D stacked DRAM-on-logic for AI workloads, recruiting design engineers in San Jose, California, as part of a strategic hiring exercise to collaborate with U.S.-based customers. The company also announced a $500 billion-plus partnership with Nvidia to build a 2-gigawatt AI factory using Nvidia Vera Rubin chips and SK Hynix HBM4, with the first factory expected online in 2027. Meanwhile, former Intel CEO Pat Gelsinger criticized HBM as a \"lousy memory,\" and SK Hynix's Hoshik Kim agreed that HBM is not the final answer.", "body_md": "# Dancing the frantic flash fandango\n\nThe flash and memory supplier world went into a frenzy of activity over the weekend, with Micron starting a feud with Apple, Anthropic asking for chips from SK Hynix, Nvidia and SK Hynix partnering, 3D DRAM pointers from SK Hynix, and CXL memory pooling from Samsung.\n\nSince SK Hynix is front and center here, let’s start with that company. Citrini analyst Jukan [posted](https://x.com/jukan05/status/2080477408478769186) that it’s developing 3D stacked DRAM. That’s because the company is [recruiting](https://job-boards.greenhouse.io/skhynixamerica/jobs/5362345008) 3D-stacked DRAM-on-logic design engineers through its U.S. subsidiary in San Jose, California. It talks about a strategic hiring exercise, saying “we are seeking talent capable of driving the co-design of 3D-stacked DRAM logic dies in close collaboration with U.S.-based customers.” That’s customers plural.\n\nWe might imagine the logic means a system semiconductor processor of some kind and it has a 3D DRAM stack layered above it. SK Hynix is also looking for [3D stacked DRAM design engineers](https://job-boards.greenhouse.io/skhynixamerica/jobs/5362335008). Integrating DRAM and logic, a single die provides faster DRAM-to-logic connectivity and a lower power draw than connecting a memory die package to a logic package; so-called package-on-package (PoP) technology.\n\nThe target devices, Jukan suggests, are ones running AI workloads and needing high memory bandwidth and low power consumption; mobile application processors for smartphones, with Apple an obvious SK Hynix customer possibility.\n\n##### SK Group and Nvidia\n\nThe two companies announced an expanded partnership, with formalized letters of intent and a $500 billion-plus value. The SK Group’s SK Telecom will become a neocloud and build a 2-gigawatt Nvidia Vera Rubin, DSX AI Factory to serve global compute demand. The Vera Rubin chips will use SK Hynix HBM4, and the first AI Factory should come online in 2027.\n\nThe pair aim to accelerate large-scale AI infrastructure development, including sovereign, physical, agentic and enterprise AI services and jointly address the increasing AI demand across the Asia-Pacific region, including South Korea.\n\nSK Hynix is also entering into a long-term AI memory partnership with Nvidia, allowing NVIDIA to secure a stable supply of next-generation AI memory, while enabling SK Hynix to increase its manufacturing output. It and Nvidia will will co-develop and optimize next-generation AI memory solutions, including HBM, for LLM training, agentic and physical AI.\n\nSK Group Chairman Chey Tae-won, said, “By leveraging SK Hynix’s AI memory and SK Telecom’s AI infrastructure capabilities, SK will collaborate with Nvidia to build a world-class AI factory, helping Korea transcend its role as a leading adopter of AI and become a global hub that drives AI innovation.”\n\n**SK Hynix, Gelsinger and HBM**\n\nFormer Intel CEO Pat Gelsinger participated in a Korea [fireside chat](https://x.com/firesidealpha/status/2081076238563897548) and criticized HBM saying: “We've heard about HBM, high bandwidth memory. And HBM is a lousy memory. And I know my memory friends are about to come on stage, and calling their baby ugly is not maybe the best way to make friends and influence people. But it's a lousy memory.\"\n\nHBM involves stacking DRAM and that creates a thermal sandwich, which is bad, is constrained by a GPU chip’s four edges, its limited shoreline, for connectivity, is power inefficient and also bit-inefficient: “for every bit that I'm creating for HBM, I've given up four bits of memory, nominally.” But “It is just the best one we have right now.\"\n\nSK Hynix's SVP and Fellow, Memory Systems Research, Hoshik Kim [agreed](https://x.com/firesidealpha/status/2081094995101241454) with Gelsinger in a qualified way: \"No, actually, I kind of agree with Pat. So HBM is not the answer.”\n\nHowever; “It's a good memory, but it's not the final answer. So actually, HBM will not solve the memory-wall problem. Memory-wall problem is an inherent AI problem, which you cannot avoid.”\n\nAnd: \"But that's the only thing we got right now to help ease this memory-wall problem, memory-bottleneck problem. But at the same time, we are working in different directions to solve this memory-wall problem with different solutions.\"\n\n**SK Hynix and Anthropic**\n\nBloomberg [reports](https://www.bloomberg.com/news/articles/2026-07-25/sk-chair-says-anthropic-asked-for-supplies-to-make-its-own-chips) that one of the top American AI developers, Anthropic, is talking to SK Hynix about having a memory chip supply for its own, in-house, AI processors. SK Group chairman Chey Tae Won said this at an San Francisco AI Summit, held at The Midway on July 2024, while Anthropic CEO Dario Amodei was also on the stage.\n\nChey Tae Won said Anthropic’s HW ambitions were remarkable. Many companies are interested in breaking Nvidia’s GPU processing dominance in the AI field. Amodei's response has not been reported.\n\n##### Samsung and CXL\n\nA Samsung [tech blog](https://semiconductor.samsung.com/news-events/tech-blog/breaking-ai-memory-limits-with-cxl-memory-pooling/) says it achieved near-DRAM performance for AI Inferencing workloads while using external CXL-connected pooled memory for KV cache offloading.\n\nIt says LLMs (Large Language Models) rely on KV Cache to store previously computed attention keys and values during inference. By reusing this information instead of recomputing it for every generated token, models can significantly reduce inference latency and computational overhead. KV Cache requirements can easily reach hundreds of gigabytes. As model sizes grow the AI processor’s memory becomes insufficient. Traditional offloading approaches based on SSDs or network-attached memory can alleviate capacity constraints, but often introduce additional latency and bandwidth overhead.\n\nCXL allows systems to scale beyond the physical limitations of traditional DRAM configurations, by enabling memory expansion through a coherent, high-bandwidth interconnect; PCIe. Multiple memory devices can be aggregated into a shared memory pool, using a CXL switch. Samsung's CMM-D (CXL Memory Module-DRAM) is designed for such memory expansion architectures.\n\nSamsung tested the performance of Nvidia RTX PRO 6000 Blackwell GPUs, its CMM-D modules connected through a CXL switch, using PCIe gen 5, and configured as a 1TB CXL memory pool, the vLLM and LMCache software stack, and host-level optimizations. The intent was to test if a CXL memory pool could support large-scale KV Cache offloading while maintaining performance comparable to DRAM. The result was that it could.\n\nIn single-GPU configurations, the optimized CXL memory pool achieved performance comparable to DRAM when used as the LMCache backend. In multi-GPU environments utilizing eight GPUs, the CXL memory pool maintained approximately 92% of DRAM performance while providing significantly greater memory capacity.\n\nThe study also compared a 512 GB DRAM configuration with a 1 TB CXL memory pool under increasing KV Cache demands. As KV Cache requirements exceeded available DRAM capacity, performance degradation occurred due to cache re-computation overhead. In contrast, the CXL memory pool maintained stable performance while accommodating substantially larger KV Cache footprints.\n\nA downloadable [white paper](https://download.semiconductor.samsung.com/resources/white-paper/Optimizing_KV_Cache_Offloading_to_CMM-D_in_a_CXL_Switch-based_Memory_Pool.pdf) describes the testing.\n\nSamsung notes “current CXL switch environments require host-level modifications, including changes to the kernel and software components such as LMCache, due to several technical considerations. Based on the performance observed in this white paper, the effectiveness of a CXL 3.0–based memory pooling architecture can be anticipated. These limitations are expected to be progressively addressed as the CXL 3.0 ecosystem matures, with the introduction of platforms such as Intel DMR, AMD Venice, and CXL 3.0 switch–based solutions.”\n\n##### Apple vs Micron\n\nCitrini analyst Jukan [cites](https://x.com/jukan05/status/2080821984385278397) a WSJ report saying Apple is lobbying the White House to let it use DRAM made by China’s CXMT in its devices; CXMT being on the USA’s Entity List preventing its use by US companies. Micron is counter-appealing, saying CXMT chip use should be prevented.\n\nHe suggests Micron CEO Sanjay Mehrotra has a long-standing grudge against Apple dating from when he was CEO of Sandisk, when Apple forced it to accept low flash prices in the then buyers’ market. Now it is a memory sellers’ market and he doesn’t, its implied, want to let Apple off the memory pricing and supply constrained hook.", "url": "https://wpnews.pro/news/dancing-the-frantic-flash-fandango", "canonical_source": "https://www.blocksandfiles.com/flash/2026/07/27/dancing-the-frantic-flash-fandango/5278903", "published_at": "2026-07-27 16:40:21+00:00", "updated_at": "2026-07-27 16:53:26.722769+00:00", "lang": "en", "topics": ["artificial-intelligence", "ai-chips", "ai-infrastructure", "ai-research"], "entities": ["SK Hynix", "Nvidia", "Apple", "Anthropic", "Samsung", "SK Telecom", "Pat Gelsinger", "Hoshik Kim"], "alternates": {"html": "https://wpnews.pro/news/dancing-the-frantic-flash-fandango", "markdown": "https://wpnews.pro/news/dancing-the-frantic-flash-fandango.md", "text": "https://wpnews.pro/news/dancing-the-frantic-flash-fandango.txt", "jsonld": "https://wpnews.pro/news/dancing-the-frantic-flash-fandango.jsonld"}}