DAC 2026: Users Are Not Waiting; DIY AI Is Now in Vogue

Samsung Electronics engineers will present a reinforcement-learning agent that tunes SoC quality-of-service settings at the DAC 2026 Engineering Track, demonstrating that major semiconductor houses are building their own AI stacks rather than waiting for EDA vendors. The DIY AI trend, which Samsung, Nvidia, and other hyperscalers are pursuing internally, creates a dilemma where each company's private work benefits itself but fails to propagate industry-wide, according to Simon Davidmann, whose framework anchors the analysis.

When my friend Simon Davidmann, whose framework anchored Part 1 of this series https://www.eetimes.com/ai-in-eda-is-real-its-now-and-its-on-show-at-dac-2026/ , laid out his agentic AI argument in recent months, one observation got less attention than his band-aid-versus-reset headline, yet it deserves more: The customers are doing it themselves. Hyperscalers and semiconductor houses are not waiting for vendors to ship finished AI products. They are building their own orchestration, their own agents, and their own models, on top of the simulation, formal, implementation, and signoff engines they already license. The EDA tools become engines; the intelligence layer above them increasingly belongs to the user. As Simon pointed out https://www.edn.com/what-is-the-eda-problem-worth-solving-with-ai/ , Samsung, Nvidia, and their peers are assembling internal AI stacks that treat vendor tools as engines beneath a domain-specific intelligence layer. But he attached a barbed caveat: Because that work stays behind corporate firewalls, it is “effective and myopic at the same time.” Each giant rebuilds similar integrations in private; the lessons never propagate to the rest of the industry—and, worse for the rest of us, the giants get to learn from all their own data, something those outside the walls can only wish for. That is Davidmann’s Dilemma from Part 1 in its purest form: every player acting rationally and the ecosystem collectively worse off for it. If you want evidence that DIY AI is now mainstream practice rather than hyperscaler exotica—and, contra Simon’s caveat, that at least some of the lessons are starting to propagate in public—the DAC 2026 Engineering Track is the closest thing we have to proof. An honest qualifier belongs here: The most secretive giants still are not presenting—you will not find Nvidia, Meta, or OpenAI walking through their internal design-AI stacks, and some of the industry’s most advanced users treat their flows as IP and stay home entirely. What the Track shows is the visible part of the iceberg. But the visible part has grown remarkably. The Engineering Track is DAC’s user conference within the conference—working engineers presenting deployed results, peer-reviewed by other engineers—and this year, it reads like a census of do-it-yourself AI. What follows is my tour of the DIY AI wave, followed by its deliberate juxtaposition: users adopting the vendors’ AI, with equally concrete numbers. Both are true simultaneously, and the tension between them is exactly where Simon’s framework earns its keep. View All https://www.eetimes.com/category/sponsored-content/ Exhibit A: Samsung teaches an RL agent to tune an SoC Start with the presentation I would use to explain the entire trend to a skeptic: On Monday morning, Samsung Electronics engineers Hyungtae Park, Rira Oh, Sanggu Kim, Hyunjae Woo, and Youngsik Kim present “Adaptive QoS Optimization for SoC Performance Enhancement Using Dueling Double Deep Q-Networks.” https://63dac.conference-program.com/presentation/?id=ENGPRES048&sess=sess262 The problem: Modern SoCs expose a thicket of quality-of-service knobs—arbitration, priorities, bandwidth allocations across many masters—and manually tuning them across varying scenarios has become intractable. Samsung’s answer: Build an execution environment that runs the SoC pre-silicon—think emulation—and set a reinforcement-learning RL agent loose in it. The agent—Deep Q-Networks with dueling and double-DQN enhancements, prioritized experience replay, the full modern RL toolkit—explores the design space against reward functions built on throughput, latency, and power and discovers QoS settings that significantly outperform manual methods. Notice the architecture of the achievement—and notice, per Part 1’s model-spectrum musing, that there is no LLM in sight: This is a user-trained optimization model, not a wrapped chatbot. The execution infrastructure that makes the exploration trustworthy comes from the EDA world; the intelligence that exploits it is Samsung’s own, purpose-built for Samsung’s architectures and Samsung’s performance targets for what they call “System Performance Verification.” That division of labor—vendor engines below, user intelligence above—is Simon’s observation rendered as a methodology paper, and it repeats across the track. The DIY AI census IBM turns agents loose on verification debug—and on tool development itself. In IBM Z hardware verification, agentic flows now automate failure triage and root-cause analysis https://63dac.conference-program.com/?post type=page&p=16&id=ENGPRES420&sess=sess267 , integrating design specifications, HDL, waveforms, coverage data, and prior issues through Model Context Protocol MCP servers, with customized agents extracting cone-of-influence logic and correlating transactions—reporting an estimated 15% to 40% reduction in manual effort on one of the most expertise-hungry tasks in the flow. A second IBM paper https://63dac.conference-program.com/?post type=page&p=16&id=ENGPRES389&sess=sess267 goes a level more meta: an agentic framework that generates EDA utilities themselves from user specifications using reusable MCP building blocks, reducing one structural-verification tool’s development from an estimated four person-weeks to under 30 minutes. Note MCP appearing twice: The connective-tissue standard from Part 1’s data-and-glue layer where Perforce https://63dac.conference-program.com/?post type=page&p=18&inst=17720131854338303388 pairs it with RAG for design-data context is showing up in user methodology papers barely a year after entering the conversation. The connective tissue is arriving. And it raises a question Simon put to me directly, worth carrying into Tuesday’s Build-versus-Buy panel: Why are the big EDA vendors not shipping these utilities themselves—and why are users such as IBM building rather than buying from the startups next door? An on-premises LLM babysits emulation regressions A flagship-SoC team from Samsung presents an unattended software-testing framework for pre-silicon emulation https://63dac.conference-program.com/?post type=page&p=16&id=ENGPRES061&sess=sess263 that pairs fast-boot virtualization with an on-premises LLM that reads kernel panics and decides: genuine software bug or non-critical bring-up artifact? The detail to savor is “on-premises”—the confidentiality requirements of semiconductor design mean the user’s DIY AI runs inside the user’s walls, on top of the vendor’s emulation platform. Another team presents an on-premises, multi-agent “Team of Experts” pipeline https://63dac.conference-program.com/?post type=page&p=16&id=ENGPRES140&sess=sess267 —a classifier agent routing to specialized sub-agents for UVM code generation, log parsing, and specification retrieval across JEDEC, LPDDR, and HBM documents—built with RAG and finetuning precisely so that no design data leaves the building. The knowledge layer gets formalized A Samsung team presents an ontology-driven knowledge graph https://63dac.conference-program.com/?post type=page&p=16&id=ENGPRES068&sess=sess265 that transforms hundreds of pages of interlinked design documents into a queryable graph feeding a Graph-RAG chatbot—the specification-engineering thread from Part 1’s front-end stage, implemented by users for users. In the POWER processor verification environment, ML-driven analysis correlates test components https://63dac.conference-program.com/?post type=page&p=16&id=ENGPRES431&sess=sess265 with coverage events and composes “super-tests” that make up 86% of recommended test cases for hard-to-hit scenarios. Implementation and analog join in Texas Instruments describes a deep-RL analog sizing tool https://63dac.conference-program.com/?post type=page&p=17&sess=sess278 —with custom reward shaping, optimizing across all PVT and Monte Carlo corners—deployed at scale with over 100 circuits optimized to signoff quality. An automotive SoC team from Renesas presents a Random Forest framework predicting die size https://63dac.conference-program.com/?post type=page&p=16&id=ENGPRES206&sess=sess262 from design specifications with R2 up to 0.95 across 1,800 RTL modules. On the Gladiator stage, a team from Samsung uses LLMs to interpret netlists and cluster DRAM peripheral cells https://63dac.conference-program.com/?post type=page&p=17&sess=sess224 for placement—expert structural knowledge written as natural-language prompts rather than rule-based code—cutting design-rule violations by 80.6%, while Samsung’s Sungsu Byun applies gradient-boosted models to switch-cell optimization https://63dac.conference-program.com/?post type=page&p=17&sess=sess297 against RedHawk-reported voltage variation. A neuro-symbolic framework presented by Cadence https://63dac.conference-program.com/?post type=page&p=18&inst=4977716620269067812 called Auto-Chk https://63dac.conference-program.com/?post type=page&p=16&id=ENGPRES210&sess=sess277 compiles natural-language signoff intent into deterministic checkers—120+ checklist items in production, 20× faster checker development. Even formal verification gets the treatment: AI-generated “helper” invariants https://63dac.conference-program.com/?post type=page&p=16&id=ENGPRES065&sess=sess266 converting bounded proofs into full closure. And one paper turns AI on the infrastructure itself https://63dac.conference-program.com/?post type=page&p=16&id=ENGPOST460&sess=sess267 , using graph neural networks and RL to forecast EDA compute needs, cutting cloud overprovisioning by 60% to 80%. Add it up, and the pattern is unmistakable: RL agents, on-prem LLMs, knowledge graphs, multi-agent pipelines, neuro-symbolic compilers—built by users, running on vendor engines, presented with deployment numbers rather than aspirations. Hold each one up to Davidmann’s Test, and the census gets even more interesting: Most of this speeds up what their teams already verified—dramatically, honestly, and with numbers. A few—the invariants that convert bounded proofs into full closure, the QoS exploration no human team could have swept—edge toward changing what can be verified at all. The juxtaposition: vendor AI, adopted and audited Now let’s look at the other half of the picture, because the same Track that documents the DIY AI wave also documents users adopting vendor AI—and, in the best Engineering Track tradition, auditing it in public. A user methodology paper on Cadence Voltus InsightAI https://63dac.conference-program.com/?post type=page&p=16&id=ENGPRES318&sess=sess276 examines AI-driven power-grid reinforcement for IR closure—and does something refreshingly honest: It presents a detailed design-impact analysis for working with the tool’s capabilities and around its limitations. That sentence is the Engineering Track’s entire value proposition in miniature. Broadcom’s APD AI team and Synopsys https://63dac.conference-program.com/?post type=page&p=18&inst=3575933958824975525 ’s RedHawk-ET team jointly present an early 3DIC thermal flow https://63dac.conference-program.com/?post type=page&p=16&id=ENGPRES310&sess=sess275 , correlated to silicon within 3°C Part 3 returns to it —vendor AI and user expertise co-developed rather than bought off the shelf. Intel https://63dac.conference-program.com/?post type=page&p=18&inst=14124970126643328419 presents its library QA framework https://63dac.conference-program.com/?post type=page&p=16&id=ENGPRES309&sess=sess271 built on Siemens https://63dac.conference-program.com/?post type=page&p=18&inst=15737075033194746030 ’s Solido Crosscheck, native checks fine-tuned alongside custom ones. An AI-driven thermal-aware placement methodology https://63dac.conference-program.com/?post type=page&p=16&id=ENGPRES120&sess=sess275 explores hundreds of constrained scenarios for 3D chiplet stacks. And in the special sessions, Sandisk’s Mariana Shenker shows production AI workflows for specification-driven development https://63dac.conference-program.com/?post type=page&p=17&sess=sess284 —the user-experience counterpart to the “Spec-Tacular ” session’s startup pitches. So which is it: users building their own or users adopting the vendors’? The Track’s answer is both, sorted by where the intelligence needs to live. Where the problem is deeply proprietary—an SoC’s QoS behavior, a company’s debug tribal knowledge, confidential failure logs—the AI is homegrown and on-premises, with vendor engines supplying the physics and the simulation truth underneath. Where the problem is common to everyone—IR closure, library QA, thermal analysis—vendor AI embedded in the platforms wins on economics. The boundary between those two zones is, I suspect, where the next five years of EDA business models get decided. Simon’s holistic reset, if it comes, will have to serve both sides of that line; Monday’s DAC Pavilion panel “Agentic AI in EDA: Who’s in Control?” https://63dac.conference-program.com/?post type=page&p=16&id=PAV101&sess=sess218 and Tuesday’s “Build vs Buy: Who Owns the Intelligence Behind Tomorrow’s Chips?” https://63dac.conference-program.com/?post type=page&p=16&id=PAV102&sess=sess222 put that exact question on stage, and Simon himself joins Wednesday’s exhibitor forum panel, “Harnessing AI for SoC Verification: Disruptive or Collaborative?” https://63dac.conference-program.com/?post type=page&p=16&id=EF111&sess=sess242 —the perfect closing argument for this article’s thesis, argued live. For the startup-side complement to these user stories, Monday’s Veriest https://63dac.conference-program.com/?post type=page&p=18&inst=15751487488218609029 -hosted exhibitor forum session, “Beyond the Hype: Innovation in AI for Chip Design and Verification,” https://63dac.conference-program.com/?post type=page&p=17&sess=sess299 showcases what the agentic layer from Part 1’s landscape https://www.eetimes.com/ai-in-eda-is-real-its-now-and-its-on-show-at-dac-2026/ is building for exactly these users. The itinerary, complete Three parts, one arc: Part 1, the landscape of who https://www.eetimes.com/ai-in-eda-is-real-its-now-and-its-on-show-at-dac-2026/ ; Part 2, the users quietly building their own intelligence on the industry’s engines; and Part 3, the sessions on creating AI chips—the end product this whole industry exists for. And if Part 1’s Expedia comparison did not convince you, here is a culinary one: Think of DAC Explorer https://dac-explorer.dac.com/ as the conference’s AI sous-chef. Hand it the ingredients you fancy: say, a base of RL, some on-premises LLMs, and a pinch of MCP, and it finds the recipe—a personalized schedule of sessions, plated and ready to export. No reservations are required, although seats at the popular sessions do go fast. Registration is at dac.com , and every session mentioned here is in the official DAC 2026 program . See you in Long Beach. Frank Schirrmeister writes about semiconductors, EDA, and system design. He serves as program chair of the DAC Engineering Track; this series is written in that capacity, not on behalf of his employer, Synopsys. Opinions are his own. Read also: Strategies for Addressing More Complex Custom Chip Design https://www.eetimes.com/strategies-for-addressing-more-complex-custom-chip-design/ How Chip Startups Are Changing the Way Chips Are Designed https://www.eetimes.com/how-chip-startups-are-changing-the-way-chips-are-designed/ AI Chips Shifting from Round to Rectangular https://www.eetimes.com/ai-chips-shifting-from-round-to-rectangular/