CXL-Connected MRAM Address AI Storage Latency

Everspin Technologies demonstrated what it calls the industry's first CXL-attached DDR4 MRAM at the SNIA Developer Conference in Santa Clara, California, using four 1-GB Everspin DDR4 MRAM modules to create a contiguous 4-GB memory space on a Supermicro server with an AMD EPYC 9355 processor and an AMD Alveo U250 FPGA card carrying a Wolley CXL 3.2 controller. Everspin VP of corporate strategy Steffen Hellmold said the platform passed MemTester and Google Stress App validation tests and that "CXL-MRAM can provide 100× lower latency than NVMe NAND SSD," positioning MRAM as a persistent cache tier between DRAM and NAND flash rather than a NAND replacement. Objective Analysis principal analyst Jim Handy said the demonstration validates using CXL as a standard way to connect new memory technologies to servers, though commercial CXL deployments remain in early stages.

The memory bottleneck in AI systems gets a lot of attention, but storage latency is a growing pain point too. Everspin Technologies thinks it can address it with what it says is the industry’s first CXL-attached DDR4 MRAM. At the SNIA Developer Conference in Santa Clara, Calif., Everspin demonstrated its combined MRAM modules with a CXL controller, creating pool of persistent memory accessible through CXL.mem semantics, which allows MRAM to act as a new tier of storage between DRAM and NAND flash. Everspin’s demo used a Supermicro server equipped with an AMD EPYC 9355 processor and an AMD Alveo U250 FPGA card incorporating a Wolley CXL 3.2 controller. Four 1-GB Everspin DDR4 MRAM modules created a contiguous 4-GB memory space. The platform passed both MemTester and Google Stress App validation tests, which Everspin said demonstrates its readiness for customer workload evaluations. In a briefing with EE Times, Steffen Hellmold, Everspin’s VP of corporate strategy, said the goal is not to position MRAM as a NAND replacement. Instead, the company said it sees the technology as a high-performance persistent cache layer. “Augment your solid-state storage with some MRAM, and you get a very high-performing combination,” he said. View All https://www.eetimes.com/category/sponsored-content/ EE Times https://www.eetimes.com/author/ee-times/ 10.05.2026 Storage bottlenecks can drive system utilization to less than 50%, Hellmold added, which can leave expensive GPUs sitting idle waiting for I/O operations to complete. “CXL-MRAM can provide 100× lower latency than NVMe NAND SSD,” Hellmold said. Hellmold said that persistent memory accessible with memory semantics rather than storage protocols can significantly accelerate checkpointing, key-value caches, and scratchpad workloads in AI systems. “If a GPU has to wait 100 microseconds or 100 nanoseconds for a checkpointing operation to complete, that determines how fast the GPU can move on to the next task,” he said. Unlike battery-backed DRAM approaches, MRAM also retains data without power, Hellmold said, which eliminates concerns associated with batteries or supercapacitors used for power-failure protection. Once touted by some vendors as a potential DRAM successor, MRAM has found more traction in niche but valuable applications where persistence, endurance, and low latency are critical. MRAM has already been used in data center storage applications for more than 15 years, serving functions ranging from journal memory to write-data buffers and caches. Memory hungry data centers, meanwhile, are not only gobbling up high volumes of HBM and DRAM https://www.eetimes.com/ai-demand-will-keep-dram-market-under-pressure/ but are also being architected to make use of a variety of memories for different tasks https://www.eetimes.com/dynamic-ai-demands-drive-memory-diversity/ , including LPDDR4, SRAM, and MRAM. Whether CXL becomes the catalyst that expands MRAM adoption https://www.eetimes.com/mram-gets-its-own-sig/ remains an open question. The emerging interconnect standard has gained momentum as hyperscalers seek memory pooling and expansion technologies, but commercial deployments remain in their early stages. “The memory shortage has greatly helped us to basically push the use case of CXL attached memory,” Hellmold said. “MRAM certainly will be very attractive as a complement.” Jim Handy, principal analyst at Objective Analysis, told EE Times in an interview that Everspin’s CXL demonstration validates the long-discussed concept of using CXL as a standard way to connect new memory technologies to modern servers. While CXL deployments to date have focused primarily on DRAM expansion and pooling, Everspin’s demonstration shows how alternative memory technologies can also benefit from the emerging ecosystem, he said. Using MRAM connected via CXL is also better than approaches that attempt to replicate NVDIMMs in CXL because it doesn’t require any big backup capacitors, Handy added. It also doesn’t require users to install specialized DIMMs directly into server memory slots, “getting a little bit too much into the bowels of the server.” MRAM’s native persistence makes it particularly attractive for handling “data in flight” that must survive power failures before being committed to SSDs or hard drives. Common applications include financial systems, gaming machines, and storage networks where preserving system state is critical, Handy said. “If they lose their status during a power outage, that’s a real problem.” The use of CXL also helps overcome one of the practical barriers that has limited broader experimentation with emerging memories. “It is cool that they put it into a CXL module,” Handy said. “It does allow pretty much anybody who wants to experiment with it to just plug it into a system and go.” Read also: Synopsys Updates CXL IP Portfolio for AI-Era Infrastructure https://www.eetimes.com/synopsys-updates-cxl-ip-portfolio-for-ai-era-infrastructure/ Xcena Cuts Data Movement to Address Memory Bottlenecks https://www.eetimes.com/xcena-cuts-data-movement-to-address-memory-bottlenecks/ CXL Adds Port Bundling to Quench AI Thirst https://www.eetimes.com/cxl-adds-port-bundling-to-quench-ai-thirst/