Co-Packaged Optics for 224Gbps+ Scale-Up: An All-In-One Overview

A technical overview of co-packaged optics (CPO) for scale-up AI compute details the packaging architectures, photonic integrated circuit (PIC) materials, laser options, and electrical IC (EIC) designs needed for mid-distance O-Band 224Gbps PAM4 links connecting trays in a rack. The post, whose research draws on ISSCC's Optical Short Course/Forum, DesignCon, and ECTC, covers packaging examples including TSMC COUPE, GlobalFoundries, Intel, and AIM Photonics, plus CPO switch examples from Ayar Labs and Lightmatter. The author will serve as a media partner for the IMAPS and SiPh Symposium in Boston, MA from Sept 28 to Oct 2, themed "Intelligent Packaging for the AI Era: Heterogeneous Integration and Photonics.

Quick Housekeeping Note: I’ll be a media partner for IMAPS and SiPh Symposium in Boston, MA from Sept 28 - Oct 2. The theme is “Intelligent Packaging for the AI Era: Heterogeneous Integration and Photonics”. These conferences cover the ground truth reality of manufacturing and test bottlenecks that constrain CPO production at scale. IMAPS: https://imaps.org/page/imaps-symposium https://imaps.org/page/imaps-symposium SiPh Summit: https://imaps.org/page/IMAPS-SiPhotonics https://imaps.org/page/IMAPS-SiPhotonics In this post I will cover a broad overview of co-packaged optics CPO primarily for scale-up as the consensus bottleneck to handle the BW of massively parallelized AI compute: Part 1: An Overview of the Packaging Architecture of Co-Packaged Optics - CPO: From Pluggable Modules to Scale-out/Scale-up - Major Components in CPO - Packaging Options of EIC and PIC - Packaging Challenges: Yield and Precision Coupling - Packaging Examples: TSMC COUPE, GF, Intel, AIM Photonics - CPO Switch Examples: Ayar Labs, Lightmatter Part 2: Light Manipulation - PIC Passive/Modulator Material Options - Conventional Solution: SiPh and Si <sub 3</sub N<sub 4</sub - Passive Routing Challenge: Coupling Light Vertically - Photonic Design Automation - Emerging Directions TFLN, BTO Part 3: Light Generation - Laser Options - 🔒InP - The Laser Substrate Material of Choice - 🔒Distributed Feedback Laser DFB - 🔒Other O-Band Lasers EML, Hybrid, Quantum Dot, multi-λ - 🔒Important Considerations in Laser Selection - 🔒Laser Form Factors OIF ELSFP, OSFP - 🔒Wavelength Division Multiplexing WDM 🔒 Part 4: EIC Architecture Options - 🔒Driver Design Considerations and Topologies for MZM, MRM, and EAM - 🔒TIA Design Considerations - 🔒Higher-Order Modulation & Simultaneous Bi-Directional Transmission - 🔒FEC options 🔒 Conclusion - CPO Ecosystem This post will bridge together the device physics, manufacturing, and circuit design of CPO into a comprehensive mental framework of technology options and tradeoffs for all engineers involved. The research for this post comes from my accumulated conference experience and insights from domain-specific experts at ISSCC’s Optical Short Course / Forum, DesignCon, and ECTC. Throughout this post I will focus mostly on technology options a system architect would consider for a mid-distance O-Band 224Gbps PAM4 CPO to connect trays in a rack along with necessary context. Both this architecture, along with variants of VCSEL-based short-reach optics, have their place to handle massive data movement in massively parallelized GPUs over the typical range of lengths within a tray and rack. One important distinction to keep in mind are the materials that are specialized for either light generation or light manipulation . I find that technologies in both domains often get mixed up with each other with InP handling both and I’ve certainly been guilty of this myself This post is intended for a broad audience for educational purposes only. All of the options discussed are not fixed in place, but what I believe to be are most common commercial implementations for practical purposes and not meant to endorse any particular vendor or topology. There are excellent alternative options to the ones I present. As always, if you’re an expert and notice a mistake, please reach out to me so I can have it promptly corrected. Part 1: An Overview of the Packaging Architecture of Co-Packaged Optics Lets start with a review of co-packaged optics in the broader optical communications landscape context. In general, there are two primary means to modulate an optical carrier: - Direct Modulation - Modulate an optical signal by turning a laser source VCSELs and DFBs on and off with an electrical signal - External Modulation - Modulate a continuously running laser source through an external modulator that alters the optical properties of the material in some way in response to an electric field electro-absorption, electro-optical, etc . My comprehensive optical communication post broadly covers these two major modulation schemes: IM-DD in pluggable transceivers has been the workhorse of data center networking for decades due to low cost, low power, and relative simplicity. However, high-speed electrical signals that travel between the ASIC and transceiver on copper are facing signal integrity challenges that makes long reach challenging. Depending on the distance the data travels, optical communications uses four primary optical bands to transport data. Rules of thumb include: - Use 850nm directly modulated VCSELs for short reach i.e. within a tray - Use O band for mid-reach datacom & CPO scale-up and scale-out - Use C and L band for telecom & coherent long-haul scale-across Since this post focuses on CPO for scale-up, we’ll mostly cover the options for external modulation in O-band . Coherent optical is its own complex beast and will be left out. CPO: From Pluggable Modules, Scale-out, to Scale-up The purpose of CPO is to minimize power dissipation and the distance signals travel on copper due to reach limits at high frequencies. CPO performs the E-O and O-E domain conversion as close to the ASIC as possible to carry the data efficiently between chips in the optical domain. CPO engines also enable lighter SerDes circuits that don’t need as sophisticated, power-hungry DSP to drive and correct signals over long copper distances. CPO was originally pitched for scale-out switch trays to overcome the crowded beachfront usage of front-panel faceplates due to DSP-based pluggable transceivers. CPO switches are connected directly to networking switch ASICs, such as Broadcom’s Tomahawk, Cisco’s Silicon One, or Nvidia’s Spectrum-X/Quantum-X. Note that CPO is not widely deployed in scale-out as of Sep 2026, but is beginning to see early, limited deployment. At DesignCon 2026 in February, Halil Cirit, AI Architect at Meta, noted that the current 224G/lane building blocks are 1.6T Optical Engines with 8 × 224G-PAM4 O-band MZM SiPh. Mach-Zehnder Modulators MZM are broadband devices, generally thermally robust, have a mature manufacturing ecosystem, and have sufficient area in large 51.2T/102.4T switch ASIC form factors. Overall, this switch has very good linearity, low distortion, and easy to integrate. However, given the massive AI data needs, CPO is emerging as the main switch solution in scale-up domains to connect massively parallelized GPUs. Porting this technology from scale-out to scale-up faces several challenges for boosting data rate and integrating alongside xPUs, including: - BW limits of SiPh ~56 - 60GHz - this is right at the limit of 224G PAM4 signals with a Nyquist frequency of 56GHz - Beachfront limits of ASICs competing with HBM and power modules - Thermal characteristics of the hot GPU - Reliability and serviceability of underlying components over the lifetime of the compute / switch tray As a result, porting existing scale-out solutions to scale-up requires a fundamental rework of the standard modulator architecture and the underlying materials. On the photonics side, the two most promising modulators are ring modulators and electro-absorption modulators due to their compact size. CPO addresses the consensus bottleneck of scale-up BW in AI data movement, but should be evaluated in the context of several other factors that can constrain data movement: - New, much larger model architectures and sparse MoE parallelism can potentially bottleneck data movements in the scale-out domain - Network contention can potentially leave compute underutilized. As OpenAI alluded to, high latency and network contention of single values that need to traverse scale-up / scale-out switches can hold up an entire parallel computation. Network contention is more destructive to spatial/dataflow architectures than temporal ones like Rubin. - The electrical domain can potentially bottleneck optical modulator performance for 448Gbps+. In order words, you can have the fastest, holy grail optical modulator and PD, but their performance is wasted if the driver / TIA can’t drive / detect signals fast enough. Often times, the EIC driver bottlenecks BW. Though scale-up BW is still the consensus bottleneck now, all three considerations are important to effectively scale together to handle future unpredictability of future model architectures and sparse MoE workloads that can escape the scale-up domain. Major Components in CPO The reason all photonic components aren’t generally monolithically integrated is because Si is a poor generator of light . Si has an indirect bandgap where electron-hole recombination requires momentum conservation via a phonon alongside energy release as a photon. Si lasers are considered a “holy grail” laser. As a result, O-band optical communications often disaggregates light generation from light manipulation because materials are often specialized for one of these purposes. Group III-IV semiconductors such as InP or GaAs only need an energy transfer to generate light. However, those materials have poor passive optical losses compared to Si and Si<sub 3</sub N<sub 4</sub . Furthermore, the processing steps for those materials tends to be incompatible with CMOS processing for EICs. In the early days of CPO, blocks were distinct chiplets and 2D integrated on a common interposer to minimize the interconnect distance between chiplets. The transmit side consists of the following blocks: - EIC Driver - Amplifies the electrical signal to the external modulator / directly modulated laser - Laser - Provides the carrier optical signal to carry modulated data at a specific wavelength. For O-band, this laser can be coming from an external ELSFP / OSFP source coupled into an external modulator, or an externally modulated DFB laser EML - PIC - The photonic integrated circuit that contains the passive optical waveguides and external modulator - Fiber s - Carries the optical signal through single-mode fibers. Fibers conventionally interface with the PIC via fiber array units FAUs utilizing V-groove arrays and edge or grating couplers. The receive side requires the following: - Photodetector - typically a PIN diode that converts optical signals to electrical current - Transimpedance amplifier TIA - amplifies this electrical current to an electrical voltage Packaging Options and Challenges Optical packaging is the single largest cost and throughput bottleneck in post-silicon assembly at high volumes. There is a host of 2.5D and 3D complex integration options to control light from an external laser source. Here we see 12 different integration techniques for PIC, EIC, and interposer. Some observations: - Option c is the most common near-term implementation because it shortens electrical paths between EIC and PIC as much as possible. This helps minimize parasitic capacitance and inductance between the driver, TIA, and optical modulators / photodetectors - Cu-Cu hybrid bonding is becoming increasingly mandatory for high-speed connections. The EIC driver/receiver BW is often limited by the parasitic capacitance the μbump inherently contains 10’s fFs . Hybrid bonding of critical connections will be mandatory to scale data throughput. - Some configurations place the EIC and PIC on opposite sides of a shared interposer . These are used for complex routing or multi-chiplet bridging, but adds cost, assembly steps, and thermal resistance Major Packaging Challenges: Yield and Precision Coupling Optical is highly sensitive to any manufacturing and packaging assembly mismatches. Optical signals really do not like to see jagged edges or discontinuities in the waveguide and interfaces that can cause optical losses and scattering, affecting laser characteristics. Packaging presents several practical challenges to manufacture CPO switches at scale: - Manufacturing tolerance of optical coupling. Attaching fiber arrays units FAUs to photonic packages with nanometer alignment tolerances at volume is a big challenge. - Detachability is a critical feature that help add to serviceability should CPO units fail in the field. Two major options include: - Direct fiber attach with v-grooves - popular for legacy optical transceivers because they are simple to align. However, these require a thick fiber cable permanently dangling that take up a lot of beachfront area. - Fiber edge-coupling with glass coupler - becoming more popular for detachability, allowing for full assembly and testing of the CPO module before being plugged in. - Bonding Yield. Hybrid bonds are almost mandatory for high-speed 448Gbps+ signals, but have inherently limited yield and should be limited only to necessary connections. Unfortunately, hybrid bonding is very unforgiving with the most mature version, W2W at 98-99% per assembly and D2W at ~90-95% per assembly. More specific yield data is not publicly available and locked behind NDAs, and I think is mainly responsible for a lot of unfounded optimism regarding the technology readiness of hybrid bonding. - Thermal Management. The CTE mismatch can create shearing / strain stresses on bumps and packaging materials. Glass is particularly sensitive due to its relatively low CTE compared to Si that places stress on the bumps - Lack of Standardization. The electrical domain has a very well defined set of tool flows and standards, but optical does not have that and almost feels like the “wild west” at times. Major organizations such as OIF help define a common set of standards such as module form factors, but these are mostly contained at the component level, not the system level. Packaging Examples Three major SiPh foundry examples include TSMC, GF, and Intel as the main commercial foundries, and AIM Photonics as the main R&D one. - TSMC COUPE Compact Universal Photonics Engine is the commercial benchmark for high volume SiPh packaging. - The COUPE PDK contains a suite of photonic devices including Si/SiN waveguides, splitters, tapers, MRRs, PD, and temp sensors. - TSMC’s SoIC-X 3D hybrid bonding is used to connect EIC and PIC, making it the default for Broadcom’s Tomahawk 6 and NVIDIA’s switches. - However, COUPE locks vendors into their ecosystem and relies on external laser sources coupled in with grating couplers. Primary high-volume suppliers are Lumentum, Coherent, and Sumitomo Electric. - Global Foundries FOTONIX https://gf.com/news-and-events/blog/next-gen-gf-fotonix-redefining-flexibility-bandwidth-upgrades-full-turnkey-support/ / SCALE https://gf.com/news-and-events/news/globalfoundries-accelerates-adoption-of-co-packaged-optics-for-advanced-ai-data-centers-with-scale-optical-module-solution/ - Unlike pure-play optical foundries, GF is positioned to enable monolithic CMOS-SiPh integration where the EIC and optical circuits are fabricated on the same 300mm Si wafer. In early 2025, it announced a $575M investment in an advanced packaging, testing, and manufacturing facility in Malta, NY to be built in multiple phases. GF has two main product lines: - FOTONIX - built on a 45nm RF SOI process that supports both CWDM and DWDM with all electrical and optical components available in the PDK. Their Gen 2 SiPh platform is proven up to 200G / λ with a clear path to 400G / λ. - SCALE - the advanced packaging platform that physically packages the FOTONIX die into the CPO engines that are compliant with standard MSAs. It contains their proprietary fiber attach topologies, including V-groove passive alignment arrays and detachable glass/fiber connectors - Intel Silicon Photonics - The most integrated approach, Intel’s OCI is positioned around heterogeneously integrated InP lasers bonded directly on the Si Wafer. - The Optical Compute Interconnect OCI tile consists of two parts: - PIC, with hybrid InP lasers, SOAs, MRM, GE photodetectors, and passives - EIC: High-speed SerDes, drivers, TIAs, PMICs, TSVs - This approach is truly fully integrated and a radical departure from competitors that rely on external, off-package lasers. However, it faces several engineering challenges for controlling laser heat dissipation that requires aggressive cooling. - AIM Photonics is a well known photonics foundry primarily focused on R&D academia, defense, and early-stage prototyping, rather than high-volume commercial manufacturing. You won’t find AIM photonics manufacturing the CPO engines at volume; it incubates such technologies for commercial production. CPO Switch Examples Notable CPO options include NVIDIA Quantum-X Photonics, Marvell/Celestial Photonic Fabric, and Broadcom TH5 and TH6. I covered NVIDIA and Marvell’s approaches in further detail, along with the physics of these modulators: Two major CPO switch solutions include: - Ayar Labs - Rather than building closed, proprietary networking switches/ OEs, Ayar Labs is positioned as the open, protocol optical I/O chiplet platform for scale-up to extend GPU-to-GPU fabrics like NVIDIA NVLink with uniform latency. Ayar Labs relies on high volume manufacturing across multiple vendors to lower single vendor lock-in risk. - Ayar Labs was founded in 2015 as a spin out of a multi-year DARPA research collaboration between MIT, UC Berkeley, and CU boulder to commercialize silicon photonics and optical chiplet technologies. - Ayar Labs has two main products: - TeraPHY - an electrical-optical PHY chiplet placed side by side with host logic dies on a shared 2.5D interposer. - It primarily uses MRMs and Ge photodetectors on GF’s monolithic 300mm platform previously discussed. - TeraPHY is protocol agnostic , so it performs the E-O conversion no matter whether the data is PCIe, CXL, UCIe, etc. - It supports 8 Tbps of bi-directional BW, which is top tier compared to 16x PCIe6 that caps out at ~1Tbps. - SuperNova - the multi-wavelength continuous wave O-Band laser in an ELSFP form factor - Supernova supports 8 to 16 wavelengths per optical port across 16 ports for 256 total optical channels power port - Note that unlike NVIDIA that is closed, proprietary, and vertically integrated, Ayar Labs maximizes interoperability and provides the plumbing , similar to ARM or Synopsys. Ayar does NOT make the host ASICs, full network switches, and pluggable optical transceivers. Vendors buy their TeraPHY and SuperNova and system integrate themselves. - Lightmatter. Unlike 2.5D packaging that Ayar Labs and Intel OCI do, Lightmatter does 3D integration of chips by mounting compute dies directly on top of a photonic interposer. This completely eliminates the shoreline density limits and caps. - Their flagship platform, Passage , stitches four tiles reticles across a 300mm wafer to deliver ~114-256Tbps of aggregate optical interconnect throughput. These optical switches are SW programmable. - This is a cross section of the Passage interposer. The middle PIC contains all of the photonic devices waveguides, modulators, PDs and TSVs . The PIC connects to the top ASIC die with with dense L1 bump arrays and connects to the substrate underneath with C4 bumps. - Passage relies on MRMs which fundamentally faces thermal control challenges . Lightmatter integrates closed loop thermal tuning circuitry to lock each ring’s resonance into its appropriate laser wavelength. However, in the future, these rings face several thermal challenges for unpredictable workloads and higher compute power, especially when the large data movement it enables adds to compute heat. Part 2: Light Manipulation: PIC Modulator Material Options Now lets talk about the two workhorse technologies for light manipulation , Silicon-on-Insulator and Si<sub 3</sub N<sub 4</sub . Note that SiPh is linguistically used as the umbrella term lumping together all technology options within CPO, though SiPh, strictly speaking, refers to silicon-on-insulator in CPO. Recall that in standard optical waveguides, the waveguide material has a higher refractive index than the surrounding oxide to ensure total internal reflection, containing the light within the waveguide. Modern workhorse SiPh relies on two materials: Silicon-on-Insulator, and Silicon Nitride Si<sub 3</sub N<sub 4</sub - Silicon-on-Insulator SOI integrates optical components onto a Si chip using standard CMOS technology. - Silicon modulates light via free-carrier plasma dispersion with MZM and ring modulators. Epitaxial GeSi supports EAM modulation and PIN junctions for photodetectors. - Silicon-on-insulator has been the go-to material of choice for 224G PAM4 faces, but faces several scaling challenges for future CPO switches: - The BW of SOI modulators is limited to 56 - 60 GHz , barely being able to handle 224G data rates operating at a Nyquist frequency of 56GHz. This doesn’t make Si the ideal material for high-speed modulation at 448Gbps. - Two-photon absorption TPA inherently limits laser power coupled in. - Silicon Nitride Si<sub 3</sub N<sub 4</sub is an insulator material that is transparent from the visible spectrum 400 nm out to the mid-infrared spectrum 4000 nm - Si <sub 3</sub N<sub 4</sub is well-suited for passive routing for the following reasons: - Low-loss optical waveguides effectively handles high-power lasers - Massive bandgap of 5 eV completely eliminates TPA - Low thermo-optic coefficient 7.5x lower than Si allows for good thermal stability when next to hot GPUs - Efficient fiber-to-chip edge coupling due to low refractive index - However, Si <sub 3</sub N<sub 4</sub is a difficult material to modulate/detect light with for two reasons: - It cannot host PN junctions or free carriers since it is an insulator - Poor active tuning range to control light with thermo-optic heaters due to a lower thermo-optic coefficient Both Si and Si<sub 3</sub N<sub 4</sub are commonly co-integrated in two layers on top of each other that serve different purposes: - Si / TFLN / InP layer handles the modulation - Si <sub 3</sub N<sub 4</sub handles the low loss, high-power routing and performs WDM multiplexing - Ge / InP layer handles photodetection One of the most challenging problems in photonic integrated circuit design is moving light vertically between layers. Grating couplers are dominant for off-chip coupling. Adiabatic directional couplers are often used for internal chip coupling between layers where waveguides “taper” to force light to move in a vertical direction to a nearby tapered waveguide as well. Optical TSVs with 45<sup o</sup mirrors are an emerging trend to transport light with several excellent ECTC 2026 papers. However, optical TSVs have very stringent alignment and cleaning requirements. Photonic Design Automation Light does not like sharp bends and waveguides have losses due to surface roughness. Routing light from a coupled-in laser to the modulator and FAU requires computationally intensive SW to model optical leakage and verify overall functionality. Ansys Lumerical https://ansys.synopsys.com/products/optics/fdtd is a dominant player in the CAD SW. Photonic design automation such as inverse design can also be employed to aid in optimizing certain sections. This has potential use, but is generally not relied upon on because generated structures generally suffers from high variability to process variation . Generated structures take a long time to optimize and often do a good job at generating compact structures in ideal environments,. However, these structures are often unsatisfying on other key performance metrics over manufacturing variability. Emerging Directions for CPO Modulation I’ll highlight a few emerging approaches for scaling data rate to 448Gbps, one is that becoming commercially viable, and another that is a “holy grail”. Note that InP EMLs is the most widely deployed material for high-speed optical modulation in pluggables and will be discussed in the next section : - TFLN - Thin-film Lithium Niobate LiNbO<sub 3</sub - widely recognized as the most promising frontrunner for next gen 224G/448G per lane modulators - Lithium Niobate LiNbO <sub 3</sub is not new and has been the workhorse of telecom fiber-optics because of no chirp and high reliability. However, legacy devices are quite large and need high drive voltage not immediately suitable for CPO. - In TFLN, a 300-500nm film of lithium niobate is bonded on a SI substrate. TFLN modulates light with the Pockels effect or the linear electro-optic effect where the refractive index changes linearly and almost instantaneously to an applied electric field. This is is because, unlike Si’s free-carrier depletion, there are no physical electrons or holes moving around. - TFLN has several advantages well-suited for CPO: - Tight electrode confinement - electrodes are 1-2um apart - Very low half-wave voltage V<sub π</sub L ~ 1.5 - 2.5 V cm to be driven by LV drivers - Can reach BWs up to 100-145GHz - However, TFLN posts a major contamination risk in front-end fabs: - Lithium is not compatible with CMOS fabs because lithium poisons silicon gate oxides and residual traces on equipment can corrupt batches of multi-billion dollar CMOS wafers. - For this reason, tier 1 fabs like TSMC won’t integrate Li into their front-end CMOS line for good reason. - As a result, TFLN optical modulators are fabricated in specialized photonic foundries physically separated from mainstream CMOS lines and then combined together with Si chips at the end. - Key players include: - Hyperlight - Commercial pure-player partners with UMC and Wavetek - NanoLN - Provides wafers with lithium niobate on insulators - Barium Titanate BTO - widely considered a “holy grail” material for CPO - BTO us a ferroelectric perovskite oxide with a very high Pockels tensor coefficient, enabling massive optical phase shifts with a small shift in electric field - BTO has several advantages: - Very low drive voltage V<sub π</sub L ~ 0.2 - 0.5 V cm , enabling direct drive from raw CMOS levels without power hungry amplifiers/drivers - Tiny footprint - Compatible with CMOS fabs - However, BTO is much less mature for the following reasons: - It requires uniform, defect free BTO films to be grown with molecular beam epitaxy - Higher waveguide optical loss 2-5dB / cm due to grain boundaries - BTO is ordinarily ferroelectric before its Curie temperature of 120 °C and needs electrical poling to maximize the electro-optic effect - BTO is being actively researched by IBM/ETH Zurich, Lumiphase https://www.lumiphase.com/ a spinout of IBM/ETH Zurich and imec. - In short, BTO has tremendous potential potential to exceed 100GHz in a compact form factor with low drive voltages and higher frequency. However, don’t forget that it also requires a comparable EIC to drive it / receive it fast enough. There are several other potential materials such as organic electro-optic OEO polymers, plasmonic, and hybrid-plasmonic modulators that are being actively researched. Part 3: Light Generation - Lasers / Light Sources External lasers specifically used for Silicon Photonics SiPh and CPO/NPO primarily use CW-WDM MSA architectures where continuous-wave CW light is fed to off-chip modulators. After the paywall the following topics will be further discussed: Part 3: Light Generation - Laser Options - 🔒InP - The Laser Substrate Material of Choice - 🔒Distributed Feedback Laser DFB - 🔒Other O-Band Lasers EML, Hybrid, Quantum Dot, multi-λ - 🔒Important Considerations in Laser Selection - 🔒Laser Form Factors OIF ELSFP, OSFP - 🔒Wavelength Division Multiplexing WDM Part 4: EIC Architecture Options - 🔒Driver Design Considerations and Topologies for MZM, MRM, and EAM - 🔒TIA Design Considerations - 🔒Higher-Order Modulation & Simultaneous Bi-Directional Transmission - 🔒FEC options