Cerebras Systems has officially introduced the CS-4, the fourth generation of its wafer-scale AI supercomputing platform, designed for frontier training and high-concurrency inference workloads. The system is engineered around three newly developed Wafer Scale Engine 3 (WSE-3) Turbo processors, housed in a ground-up redesign called the Nexus rack-scale platform. Cerebras claims the system delivers up to 30 times the inference performance of GPU-based solutions, a figure the company bases on GPT-OSS-120B, where it cites more than 4,400 tokens per second per user, along with a 10-fold increase in throughput per watt compared to the previous-generation CS-3.
The CS-4 is designed to address the systemic scaling limitations inherent in discrete multi-node GPU clusters, where inter-chip communication, power conversion losses, and thermal limits frequently throttle sustained compute efficiency. Cerebras positions the platform to serve both extremes of the inference workload spectrum, delivering the sub-millisecond response times required for complex agentic workflows and interactive reasoning, while providing the aggregate capacity that hyperscalers need to maximize compute density per gigawatt.
Interconnect fabric improvements are central to the platform’s multi-processor scaling capabilities. The CS-4 reduces wafer-to-wafer interconnect latency to as low as 2 microseconds, enabling multi-wafer fabrics to operate with near-monolithic cohesion. This ultra-low-latency fabric enables the CS-4 to sustain generation speeds exceeding 1,000 tokens per second on models with more than 10 trillion parameters, closing the historical performance gap in which scaling up the parameter count severely compromised interactive token delivery rates.
Nexus Rack Architecture and the Wafer-Scale Backpack #
A major engineering transition in the CS-4 is the Cerebras Nexus Platform Architecture, a modular rack implementation built around independent compute, power, and I/O domains. Compute density is anchored by a newly designed, rear-mounted Wafer-Scale Backpack that connects vertically to the primary power array. Each backpack is a self-contained unit that houses direct-to-chip liquid-cooling manifolds, point-of-load power-conversion stages, high-speed networking paths, and onboard control electronics located directly behind the silicon wafer. By isolating the core compute layer from the bulk power distribution frame, Cerebras reduced the system component count by 50 percent, increased automated assembly by 60 percent, and compressed data center deployment timelines to mere hours.
Power delivery efficiency has been improved by relocating the DC-to-DC voltage regulation modules 100 times closer to the silicon boundary than in typical server board implementations. This point-of-load arrangement reduces resistive power distribution network (PDN) losses and allows the Nexus frame to deliver twice the power to each WSE-3 Turbo processor, enabling higher sustained clock frequencies without thermal throttling.
The I/O subsystem has also been expanded with a programmable Wafer I/O Module that doubles edge-to-edge fabric bandwidth while reducing transit latency. System networking operates in two modes: standard RoCE v2 (RDMA over Converged Ethernet) interfaces for low-latency fabric attachment to legacy enterprise networking and third-party accelerator nodes, and proprietary Direct Wafer Links that provide direct, switch-free interconnect paths across adjacent systems within and between racks.
CS-4 and WSE-3 Turbo Specifications #
CS-4 SYSTEM | | | Architecture | Active power rack with three modular compute backpacks | | Wafer Scale Engines | 3x WSE-3 Turbos per system | | AI Compute | 750 PFLOPS* | | Memory Bandwidth | 129.6 PB/s | | On-chip Fabric Bandwidth | 160.5 PB/s | | I/O Bandwidth | 7.2 Tbit/s | | I/O Latency | 2 microseconds | WSE-3 TURBO (PER WAFER) | | | Transistors / Silicon | 4 trillion transistors; 46,225 mm2, TSMC 5nm | | AI Cores / On-Chip SRAM | 900,000 cores; 44 GB SRAM | | AI Compute | 250 PFLOPS* | | Memory Bandwidth | 43.2 PB/s | | On-chip Fabric Bandwidth | 53.5 PB/s | | I/O Bandwidth | 2.4 Tbit/s | *AI compute shown as sparse FP16 |
Disaggregated Inference and Availability #
Architecturally, the CS-4 is built with native support for disaggregated inference topologies. In enterprise and cloud environments, operators can decouple the computational phases of inference by using specialized external prefill accelerators, such as AMD Helios or AWS Trainium, to ingest prompt contexts and build model states. The compute-bound KV cache is then routed over high-speed links to the CS-4’s massive SRAM fabric for ultra-low-latency autoregressive token generation.
Cerebras confirmed that initial production deployments and shipments of the CS-4 platform are set to begin this quarter.