# Celera raises $30M to automate custom analog chip design > Source: > Published: 2026-08-26 02:07:46+00:00 # Celera raises $30M to automate custom analog chip design **Maverick Silicon solely funded the Series B, one year after its $20M Series A, as Celera expands engineering in California and Portugal.** By [RuntimeWire Staff](/author/runtimewire-staff) ยท Published Primary source: [PR Newswire](https://www.prnewswire.com/news-releases/celera-semiconductor-announces-the-closing-of-a-30m-series-b-financing-round-302858003.html) ## Why it matters Analog design remains one of chipmaking's most manual bottlenecks. Celera is using $30M to prove digital twins can support a full chip supplier, extending AI automation beyond standalone EDA software. [Celera Semiconductor](https://celerasemi.com/?ref=runtimewire) said it [closed a $30 million Series B on August 25](https://www.prnewswire.com/news-releases/celera-semiconductor-announces-the-closing-of-a-30m-series-b-financing-round-302858003.html?ref=runtimewire), fully funded by [Maverick Silicon](https://www.mavericksilicon.com/?ref=runtimewire), to accelerate its AI-assisted analog-chip design platform and customer projects. The financing gives founder Calum MacRae and CEO Patrick Brockett more capital to pursue an old semiconductor ambition: capturing expert analog designers' judgment in reusable software. Celera plans to spend the money on its design-automation roadmap and customer projects while adding engineers in California and Portugal. According to [Brockett's SemiWiki interview](https://semiwiki.com/ceo-interviews/336896-ceo-interview-pat-brockett-of-celera/?ref=runtimewire), he joined Celera as CEO in 2023 after advising Celera for about four years. He previously held senior roles at Texas Instruments and National Semiconductor, then ran programmable-analog chipmaker Summit Microelectronics, which Qualcomm acquired for $350 million. That background makes Brockett the commercialization operator behind MacRae's technical thesis. MacRae has spent more than 25 years working on semiconductor power design and founded Celera around the view that analog development remained too manual to meet growing demand. ### Turning analog expertise into software Digital chip development has benefited for decades from abstractions and automated tooling. Analog circuits remain sensitive to device physics, process variation, temperature, voltage and the physical layout of components. Engineers repeatedly simulate and adjust designs across those variables, making scarce human experience a constraint on schedules. Celera's answer is Nesto, a patented library of digital twins representing analog functions. Celera combines those models with behavioral modeling, synthesis, verification and layout algorithms. The intended output is a finished custom or standard analog product, supplied through external foundry, assembly and testing partners. Celera is building a chip supplier whose internal production system runs on design automation. MacRae described the commercial destination in Celera's [August 5, 2025 Series A announcement](https://www.prnewswire.com/news-releases/celera-semiconductor-announces-20-million-series-a-equity-investment-from-maverick-silicon-to-revolutionize-analog-chip-market-through-ai-driven-automation-302521199.html?ref=runtimewire): "We believe real-time analog development is no longer a dream. It's a roadmap to 2030." Celera says the system cuts development cycles by 10x, and Brockett told [SemiWiki](https://semiwiki.com/ceo-interviews/336896-ceo-interview-pat-brockett-of-celera/?ref=runtimewire) that Celera targets custom analog-chip delivery in roughly four months or less. The strongest public evidence arrived in March 2025, when Celera began [sampling a high-voltage buck converter](https://www.prnewswire.com/news-releases/celera-samples-the-first-ever-analog-ic-completely-designed-by-software-302399142.html?ref=runtimewire) that it said had moved from specification to manufacturing release in days. [eeNews Europe reported](https://www.eenewseurope.com/en/celera-samples-analog-ic-designed-by-ai/?ref=runtimewire) that the device converted 60 volts to 3.3 volts and targeted a 130-nanometer BCD process at Vanguard International Semiconductor. The converter established that Celera's automated flow could produce a physical sample. Volume manufacturing, qualification and repeatability across multiple customers will determine whether the same workflow can support a durable semiconductor supplier. Celera has not attached revenue, production-volume or customer-count figures to the Series B announcement, so its development-speed claim remains the primary operating metric available outside Celera. ### The round buys engineering capacity The [June acquisition](https://www.prnewswire.com/pt/comunicados-de-imprensa/celera-semiconductor-acquires-portugal-based-silicongate-a-global-leader-in-analog-ic-design-302792103.html?ref=runtimewire) of Portugal-based [SiliconGate](https://www.silicongate.com/en?ref=runtimewire) added a product-development and design-automation team and a catalog of more than 900 silicon-proven IP designs, according to Celera's announcement. Celera had worked with SiliconGate before buying it and plans to expand the Portuguese operation into a center for analog product development and design automation. The Series B therefore finances added human expertise alongside the software intended to multiply that expertise. The Series B announcement identifies [Helen Song as Celera's CTO](https://www.prnewswire.com/news-releases/celera-semiconductor-announces-the-closing-of-a-30m-series-b-financing-round-302858003.html?ref=runtimewire). Song said Celera's California operation has expanded the range of power-management applications it can address. That focus puts Celera close to the power systems required by data centers, vehicles, industrial equipment, consumer devices and other hardware where digital processors still depend on analog circuitry to manage voltage, current and signals. ### One backer, two consecutive rounds Maverick Silicon supplied the entire Series B and is Celera's largest investor. The investment unit, part of Maverick Capital, focuses on private chip, hardware and software businesses serving rising compute demand. Maverick also funded Celera's $20 million Series A on August 5, 2025. Together with Celera's [announced $3 million seed round](https://www.prnewswire.com/news-releases/groundbreaking-ai-based-software-automation-platform-for-chip-development-secures-3m-investment-300921413.html?ref=runtimewire) in 2019, publicly announced rounds total at least $53 million. Celera did not publish a valuation for the Series B. A sole-investor follow-on gives Celera committed capital without assembling a new syndicate. It also concentrates the financing judgment with a backer already exposed to Celera's execution. Maverick is effectively funding Celera's move from an automated design demonstration toward a larger product-development and delivery operation. The competitive pressure is arriving from established design-software vendors as well. On August 25, the same day Celera disclosed its Series B, [Synopsys introduced AI-powered analog layout synthesis](https://www.synopsys.com/blogs/chip-design/analog-layout-synthesis-ai.html?ref=runtimewire) within ASO.ai and Custom Compiler. Synopsys said five customers were deploying the flow in production systems and reported 3x faster layout implementation in early deployments. Celera has chosen a heavier model. Synopsys sells tools to chip designers; Celera intends to deliver the resulting analog chips. That approach gives Celera control over the customer outcome and adds responsibility for manufacturing handoffs, qualification, packaging, testing and delivery. The $30 million round funds MacRae's original belief that analog expertise can be encoded and reused, with Brockett building the organization needed to sell the resulting silicon. The next proof point will come from repeated customer products reaching production on the schedules Celera says its automation can deliver.