{"slug": "can-you-reverse-engineer-an-asic", "title": "Can you reverse engineer an ASIC?", "summary": "Jane Street has released a new puzzle challenging participants to reverse engineer an ASIC from its GDS layout, recover the netlist, determine the chip's purpose, and find a hidden string output. The puzzle, which closes on September 4, 2026, includes sample inputs and outputs, and participants are asked to submit their answers via a Google Form. Jane Street encourages collaboration but prohibits posting spoilers until after the deadline.", "body_md": "Earlier this year we published a\n[puzzle](https://blog.janestreet.com/can-you-reverse-engineer-our-neural-network/) that\nhanded you a complete neural network and asked you to figure out what it did. The response\nwas great, so we’ve made another one! This time, we’re going much deeper down the tech\nstack.\n\nFor this puzzle we’ve designed a chip, but we’re only giving you the layout.\n\n## A crash course in how chips get made\n\nModern chips start life as code. A hardware designer describes a circuit in a hardware\ndescription language like Verilog, which gets *synthesized* into a netlist of logic\ngates—NANDs, NORs, XORs, flip-flops. Then electronic design automation tools place and\nroute those gates: they pick a physical location for every gate on the die and draw the\nmetal wires that connect them, across many stacked routing layers connected by vias. The\nend result is a GDS file: a geometric description of every polygon on every layer of the\nchip, from the transistors that do the actual logic to all the metal on top of them.\nThat’s the file a foundry such as Intel or TSMC uses to fabricate the physical silicon.\n\nThe GDS is, in a very real sense, the chip. Everything the circuit does is in there. The tricky part: nothing is labeled!\n\n## The puzzle\n\nWe’ve designed an ASIC, and we’re giving you its final mask: all of its metal, routing, and active transistor layers, along with some sample inputs and outputs.\n\nYour job is to reverse engineer it. First, recover a netlist from the layout. Then figure out the circuit’s true purpose. And then comes the puzzle within the puzzle: once you understand what the chip does, use it to tease out the output it’s looking for, and find the string value that’s your final answer.\n\nYou can find everything you need\n\n[here].Some pointers for getting started:\n\n- The circuit is physically arranged to hint at its functionality, so look closely at the layout!\n- There is one section of the design that is used to generate the output but does not affect the\n`[success]`\n\noutput. You can safely ignore it for the initial reverse-engineering steps.- You’ll need to come up with a way to simulate the underlying circuit to test your solution and get the final output!\n- You’ll know you have the correct solution when the\n`[success]`\n\noutput signal goes high. Don’t forget to toggle`[rst_n]`\n\nbefore each input attempt.- We hid a few fun Easter eggs in the circuit and in the repository (including in parts you don’t need to look at to solve the main puzzle), see if you can spot them once you’re done with the puzzle.\n\nOnce you figure it out, submit your answer\n[here](https://docs.google.com/forms/d/e/1FAIpQLScNCnfZ1wC4HbARwynUZ25EKZyqJIzXM_5H5aHom-QeAhE6FA/viewform?usp=sharing&ouid=113383508758462277069)\nalong with a brief description of how you did it. Submissions close on September 4th, 2026.\n\nFeel free to collaborate with friends on the puzzle, but please refrain from posting spoilers (or a full writeup) online until the submissions are closed. If you do publish your solution (on a personal blog or repository) after submissions are closed, email us and we may include the link in our follow-up post!\n\nPlease don’t feed the puzzle files directly into an AI tool, nor use it to generate your writeups. Feel free to use AI for writing any scripts or code you may need as part of solving the puzzle, though! It’s also fair game to use AI to work through the warm-up puzzle, see below.\n\nIf you have questions as you go, please reach out to\n[asic-puzzle@janestreet.com](mailto:asic-puzzle@janestreet.com) — we can’t give hints, but\nwe’re happy to help otherwise.\n\nWe’ll feature the most interesting writeups and techniques in a follow-up post, and send swag for our favorite solutions.\n\n## A warm-up\n\nIf you’ve never opened a GDS file before, don’t worry: most people haven’t either. To help you get started, we’re providing a small worked example: a simple binary adder, with its Verilog source, its gate-level netlist, and the resulting GDS. You can use it to get familiar with how a circuit maps onto a layout, and to test any tools you build before pointing them at the real puzzle.\n\nThe warm-up files are available in the [puzzle repository](https://github.com/janestreet/asic-puzzle-2026).\n\nEverything you need is free and open source: the design uses an open-source PDK, and tools\nlike [KLayout](https://www.klayout.de/) or [Magic\nVLSI](https://github.com/rtimothyedwards/magic) will happily open the GDS and let you poke\naround the layers.\n\n## And a bigger challenge is coming\n\nConsider this puzzle a warm-up of its own. Later this year we’ll be launching a competition where, instead of reverse engineering our chip, we’ll challenge you to design your own - and the most interesting entries will actually get fabricated, so you can test your chip in real life.\n\nStay tuned—we’ll announce the details here on the blog in the coming months.\n\n## Hardware at Jane Street\n\nThe hardware team at Jane Street designs FPGAs and ASICs that run some of the fastest trading systems in the world, and the day-to-day work is full of puzzles just like this one: staring at a sea of gates, timing reports, or waveforms and slowly teasing out what’s really going on. These problems are hard in a way that’s deeply satisfying to solve, and honestly, it’s a big part of why we like working here.\n\nIf that sounds intriguing, some ways of learning more:\n\n- Check out our hardware (FPGA and\nASIC)\n[internships](https://www.janestreet.com/join-jane-street/position/8624440002/)and[full-time](https://www.janestreet.com/join-jane-street/position/8646893002/)roles. - Read about\n[Hardcaml](https://hardcaml.org/)(our open-source OCaml hardware design libraries) - On the academic side, read about our\n[visiting researcher](https://www.janestreet.com/join-jane-street/programs-and-events/visiting-researcher/)and[graduate fellowship](https://www.janestreet.com/join-jane-street/programs-and-events/graduate-research-fellowship/)programs.\n\nIf you just want to stay in touch, you can fill out [this form](https://bit.ly/4lEqiqb).", "url": "https://wpnews.pro/news/can-you-reverse-engineer-an-asic", "canonical_source": "https://blog.janestreet.com/can-you-reverse-engineer-an-asic/", "published_at": "2026-08-05 00:00:00+00:00", "updated_at": "2026-08-09 12:58:12.012686+00:00", "lang": "en", "topics": ["ai-research"], "entities": ["Jane Street", "Intel", "TSMC"], "alternates": {"html": "https://wpnews.pro/news/can-you-reverse-engineer-an-asic", "markdown": "https://wpnews.pro/news/can-you-reverse-engineer-an-asic.md", "text": "https://wpnews.pro/news/can-you-reverse-engineer-an-asic.txt", "jsonld": "https://wpnews.pro/news/can-you-reverse-engineer-an-asic.jsonld"}}