{"slug": "budget-pcie-5-0-16x-8-card-baseboard-build", "title": "Budget Pcie 5.0 16x, 8 Card Baseboard Build", "summary": "A user who purchased 8 R9700 GPUs is asking for advice on the cheapest way to build a PCIe 5.0 x16 tensor-parallel rig for running TP8 inference on ~200GB models, proposing a single Microchip Switchtec PM50100 100-lane Gen5 switch with 8 lanes per GPU and a Ryzen host with 64GB DDR5 RAM. The user cited the GitHub project local-inference-lab/rtx6kpro topology document as inspiration, contacted Guva Systems for a quote on a true 16-lanes-per-GPU switch, and is targeting a vLLM deployment on Qwen3.8-Next-Flash or quantized GLM5.3-Flash.", "body_md": "Hey all, posing the question up front: what’s the cheapest way to get a high scaling efficiency tensor parallel rig for 8 GPUs?\n\nSo, I recently impulse bought 8x r9700 with the plan to run tensor parallel tp8 on ~200GB models. It seems like for inference performance the best implementation would be to optimize for low latency and decent bandwidth through a pcie 5.0 fabric where p2p communications never hit the cpu. I’m thinking on skimping on the host as a result (cheapest cpu+mobo that exposes a pcie 16x 5.0 slot and 64gb ram).\n\nI’m looking at the githib project “local-inference-lab/rtx6kpro/blob/master/hardware/topology.md” for inspiration using a single Microchip Switchtec PM50100 running 8x lanes per gpu flike this:\n\nRyzen host (64gb ddr5 ram, cheap mobo + processor)\n\n│\n\nPCIe 5.0 x16 slot\n\n│\n\nx16 → 2× MCIO x8 card\n\n│\n\n▼\n\n┌────────────────────┐\n\n│ C-Payne PM50100    │\n\n│ 100-lane Gen5      │\n\n│ switch             │\n\n└────────────────────┘\n\n│ │ │ │ │ │ │ │\n\nx8 each over MCIO\n\n│ │ │ │ │ │ │ │\n\n▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼\n\nPCIe x16 mechanical\n\nendpoint adapters\n\n│ │ │ │ │ │ │ │\n\n▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼\n\nR9700 × 8\n\nAnd housing all of the bits in a small cheap gpu cluster housing like a MM-A515-CPW and swapping the electronics.\n\nI reached out to guva systems to see if I could get a quote for a true 16x lanes per gpu switch since thats a clear optimization option, but I’m unsure what the performance unlocks for vllm optimization would be.\n\nI’m a bit of a greenbeard in this area though, so I could use advice on hardware choice optimizations really matter for a vllm-radiance deployment on qwen3.8-next-flash or quantized glm5.3-flash like I am currently targeting.\n\n \n\n \nJust realized the title is now misleading to the post content and I can’t edit it, I wandered a bit while researching this post.", "url": "https://wpnews.pro/news/budget-pcie-5-0-16x-8-card-baseboard-build", "canonical_source": "https://forum.level1techs.com/t/budget-pcie-5-0-16x-8-card-baseboard-build/256602#post_2", "published_at": "2026-09-18 19:19:18+00:00", "updated_at": "2026-09-18 19:24:08.317045+00:00", "lang": "en", "topics": ["ai-infrastructure", "ai-chips"], "entities": ["R9700", "Microchip Switchtec PM50100", "Guva Systems", "local-inference-lab/rtx6kpro", "vLLM", "Qwen3.8-Next-Flash", "GLM5.3-Flash", "MM-A515-CPW"], "alternates": {"html": "https://wpnews.pro/news/budget-pcie-5-0-16x-8-card-baseboard-build", "markdown": "https://wpnews.pro/news/budget-pcie-5-0-16x-8-card-baseboard-build.md", "text": "https://wpnews.pro/news/budget-pcie-5-0-16x-8-card-baseboard-build.txt", "jsonld": "https://wpnews.pro/news/budget-pcie-5-0-16x-8-card-baseboard-build.jsonld"}}