{"slug": "broadcom-adds-furiosaai-for-custom-ai-accelerators", "title": "Broadcom Adds FuriosaAI for Custom AI Accelerators", "summary": "Broadcom added South Korea's FuriosaAI to its roster of partners building AI accelerators on Broadcom's packaging and networking technology. FuriosaAI claims its third-generation processor will be fabricated on 2nm and use dual-layer HBM4 or HBM4e memory enabled by Broadcom's advanced multi-die packaging. The deal positions Broadcom's 3.5D XDSiP packaging and Tomahawk 6 switches as key enablers for chiplet-based AI accelerators scaling beyond eight chips.", "body_md": "# Broadcom Adds FuriosaAI for Custom AI Accelerators\n\nBroadcom has added South Korea's **FuriosaAI** to its roster of partners building AI accelerators on Broadcom's packaging and networking technology, The Register reports. According to The Register, FuriosaAI claims its third-generation processor will be fabricated on **2nm** and will use \"dual layer\" **HBM4** or **HBM4e** memory enabled by Broadcom's advanced multi-die packaging. The Register also reports that FuriosaAI's third-gen parts will use Broadcom Ethernet and PCIe products to support systems exceeding eight chips, implying use of high-radix switches such as Broadcom's **Tomahawk 6 (TH6)**. The piece situates the deal alongside Broadcom's **3.5D XDSiP** packaging, which disaggregates compute, memory, and I/O into chiplets assembled with hybrid bonding, and notes AMD is tunneling **UALink** over Ethernet in some OEM implementations, per The Register.\n\n### What happened\n\nBroadcom has added **FuriosaAI** to its list of partners building AI accelerators that leverage Broadcom's packaging and networking technology, The Register reports. According to The Register, FuriosaAI claims its third-generation processor will be fabricated on **2nm** process nodes and will use \"dual layer\" **HBM4** or **HBM4e** memory made possible by Broadcom's advanced packaging. The Register further reports FuriosaAI plans to use Broadcom's Ethernet and PCIe products to support systems exceeding eight chips, which implies the use of high-radix switches such as Broadcom's **Tomahawk 6 (TH6)**. The Register frames this collaboration alongside Broadcom's **3.5D XDSiP** packaging approach, which assembles disaggregated chiplets using 3D bonding techniques.\n\n### Editorial analysis - technical context\n\nMulti-die system-in-package approaches, like the **3.5D XDSiP** described by The Register, reduce the need to design monolithic SoCs by enabling separate chiplets for compute, memory, and I/O. Industry-pattern observations: companies pursuing chiplet-based accelerators commonly target advanced packaging plus high-bandwidth memory to trade integration complexity for faster time-to-market and modular scalability. Hybrid bonding and stacked HBM variants are central to achieving the high memory bandwidth required for inference-heavy workloads, while Ethernet-based fabrics are increasingly considered for scaling beyond a single package.\n\n### Industry context\n\nIndustry-pattern observations: Broadcom's packaging and switch portfolio has become a glue layer for multiple AI hardware stacks, according to public coverage. The Register's mention of AMD tunneling **UALink** over Ethernet, and OEMs using Broadcom TH6 switches, highlights an industry trend where Ethernet is being explored as a viable alternative to proprietary scale-up interconnects like NVLink for certain deployments. For practitioners, that shifts some system-level design trade-offs toward standard networking technologies and off-the-shelf switch silicon.\n\n### What to watch\n\n- •Product announcements or datasheets from\n**FuriosaAI** confirming the process node, memory topology, and packaging specifics. - •Evidence of production systems using Broadcom TH6 or similar switches to interconnect multiple multi-die packages.\n- •Third-party performance or interoperability tests showing how Ethernet-based scale-up compares to NVLink-style interconnects for large inference clusters.\n\n## Scoring Rationale\n\nThis is a notable infrastructure development: Broadcom's packaging and switch portfolio enabling a startup's 2nm, HBM4-based accelerator matters for hardware architects and system integrators. It is not an industry-shifting release, but it reinforces chiplet and Ethernet trends relevant to practitioners.\n\nPractice with real Ad Tech data\n\n90 SQL & Python problems · 15 industry datasets\n\n[Active Search Campaigns by BudgetEasy](/problems/sql/active-search-campaigns-by-budget)\n\n[High CPC Clicks & Poor Landing PagesMedium](/problems/sql/high-cpc-clicks-poor-landing-page)\n\n[Campaign ROAS by Attribution ModelHard](/problems/sql/campaign-roas-by-attribution-model)\n\n250 free problems · No credit card\n\n[See all Ad Tech problems](/problems/datasets/adtech)", "url": "https://wpnews.pro/news/broadcom-adds-furiosaai-for-custom-ai-accelerators", "canonical_source": "https://letsdatascience.com/news/broadcom-adds-furiosaai-for-custom-ai-accelerators-e1c370f8", "published_at": "2026-05-27 15:21:59.552011+00:00", "updated_at": "2026-05-27 15:22:02.825235+00:00", "lang": "en", "topics": ["ai-chips", "ai-infrastructure", "ai-startups", "artificial-intelligence"], "entities": ["Broadcom", "FuriosaAI", "The Register", "HBM4", "HBM4e", "Tomahawk 6", "3.5D XDSiP", "UALink"], "alternates": {"html": "https://wpnews.pro/news/broadcom-adds-furiosaai-for-custom-ai-accelerators", "markdown": "https://wpnews.pro/news/broadcom-adds-furiosaai-for-custom-ai-accelerators.md", "text": "https://wpnews.pro/news/broadcom-adds-furiosaai-for-custom-ai-accelerators.txt", "jsonld": "https://wpnews.pro/news/broadcom-adds-furiosaai-for-custom-ai-accelerators.jsonld"}}