Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits

Researchers introduced DeepSeq3, a hierarchical framework that abstracts sequential circuits into fine-grained combinational subgraphs and a high-level Super-Node Graph, using a dual Graph Neural Network architecture with state-centric pre-training. Demonstrated on large-scale benchmarks, DeepSeq3 reduced bounded model checking solving time by 18% while guaranteeing correctness, addressing scalability and temporal dynamics in circuit representation learning for Electronic Design Automation.

arXiv:2608.28188v1 Announce Type: new Abstract: Circuit Representation Learning CRL offers a powerful paradigm to guide and optimize core Electronic Design Automation EDA tasks, but its practical adoption is hindered by the immense scale of industrial netlists and a failure to explicitly model register-level temporal dynamics. To overcome these barriers, we introduce DeepSeq3, a novel hierarchical framework that abstracts circuits into a two-level representation: fine-grained combinational subgraphs partitioned by flip-flops FFs , and a high-level Super-Node Graph SNG that models the register-transfer structure. A dual Graph Neural Network GNN architecture learns representations at both levels, capturing local Boolean logic and global state transitions. Crucially, we introduce a state-centric pre-training scheme that predicts the reachability between FF states, endowing the model with a deep understanding of temporal behavior. Demonstrated on large-scale benchmarks, DeepSeq3's approach yields superior scalability and richer representations, reducing bounded model checking BMC solving time by 18% while guaranteeing correctness.