{"slug": "bern2edge-a-neurosymbolic-compiler-for-edge-deployment-via-bernstein-polynomial", "title": "Bern2Edge: A Neurosymbolic Compiler for Edge Deployment via Bernstein Polynomial Networks", "summary": "Researchers introduced Bern2Edge, a neurosymbolic compiler that converts pretrained feed-forward neural networks into hardware-efficient Bernstein polynomial networks for edge deployment. On an AMD Xilinx KV260 FPGA, Bern2Edge achieved up to 99.8% latency reduction and 95.2% BRAM reduction relative to a W8A8 quantized teacher while maintaining accuracy within 0.5 percentage points, and up to 2.12 percentage-point accuracy improvement over ReLU under identical compression constraints. The framework also offers a symbolic rule-based path that reduces DSP usage by up to 89.0% at a cost of 1.5 percentage points in total accuracy.", "body_md": "arXiv:2608.20497v1 Announce Type: new\nAbstract: Deploying high-accuracy neural networks on resource-constrained edge devices remains challenging, as existing approaches treat training, compression, and hardware synthesis as separate stages, leaving a gap between software-trained models and efficient end-to-end deployment with limited support for interpretability. We propose Bern2Edge, an end-to-end framework that uses knowledge distillation to convert a pretrained teacher feed-forward network into hardware-efficient representations via Bernstein polynomial activations. This representation enables two deployment paths: (i) a high-fidelity LUT-based realization that preserves model fidelity under compression, and (ii) a symbolic rule-based representation derived from Bernstein activation geometry, enabling interpretable inference with explicit input-space constraints. The resulting BNNs achieve up to 2.12 percentage-point (pp) accuracy improvement over ReLU under identical compression constraints. At the system level, Bern2Edge achieves up to 99.8% latency reduction and 95.2% BRAM reduction relative to a W8A8 quantized teacher on an AMD Xilinx KV260 FPGA, while maintaining accuracy within 0.5 pp, and further deploys on a low-power Spartan-7 XC7S15 FPGA. The rule-based path reduces DSP usage by up to 89.0% at a cost of 1.5 pp in total accuracy.", "url": "https://wpnews.pro/news/bern2edge-a-neurosymbolic-compiler-for-edge-deployment-via-bernstein-polynomial", "canonical_source": "https://arxiv.org/abs/2608.20497", "published_at": "2026-08-24 04:00:00+00:00", "updated_at": "2026-08-24 04:15:21.713057+00:00", "lang": "en", "topics": ["artificial-intelligence", "machine-learning", "neural-networks", "ai-infrastructure", "ai-research"], "entities": ["Bern2Edge", "AMD Xilinx KV260", "Spartan-7 XC7S15", "Bernstein polynomial networks"], "alternates": {"html": "https://wpnews.pro/news/bern2edge-a-neurosymbolic-compiler-for-edge-deployment-via-bernstein-polynomial", "markdown": "https://wpnews.pro/news/bern2edge-a-neurosymbolic-compiler-for-edge-deployment-via-bernstein-polynomial.md", "text": "https://wpnews.pro/news/bern2edge-a-neurosymbolic-compiler-for-edge-deployment-via-bernstein-polynomial.txt", "jsonld": "https://wpnews.pro/news/bern2edge-a-neurosymbolic-compiler-for-edge-deployment-via-bernstein-polynomial.jsonld"}}