# Astera Labs unveils next-gen CXL controllers to accelerate agentic AI workloads > Source: > Published: 2026-09-15 13:00:37+00:00 Astera Labs unveiled the next generation of its Leo Compute Express Link (CXL) smart memory controllers. The vendor added a trio of devices, with the high-end X-Series touted for offloading [key-value (KV) cache](https://www.sdxcentral.com/analysis/why-kv-cache-is-key-to-ai-memory-woes/) for high-intensity AI workloads. Paired with Astera’s [Scorpio](https://www.sdxcentral.com/news/astera-labs-debuts-scorpio-switches-to-power-single-hop-ai-scale-up/) network switch silicon, it’s designed to provide larger cache capacity with low-latency access for agentic AI inference applications. Astera also unveiled the second generation of its E-and P-series controllers to boost both central processing units (CPUs) and rack-scale memory. The E-series provides direct CPU-attached memory expansion, adding extra capacity while reducing the need for an additional socket. The second-generation P-series pools memory across rack-scale platforms, reducing server over-provisioning to maximize available capacity. Smart memory controllers are essentially infrastructure add-ons, providing CPUs and graphics processing units (GPUs) with the means to connect to additional memory capacity for an extra oomph. They keep accelerators from idling by increasing the memory bandwidth available to processing cores. “Agentic AI is where the economics of AI infrastructure are being decided and those economics depend on putting every usable gigabyte of memory to work,” Thad Omura, SVP of Astera’s compute connectivity group, noted. “The enhanced Leo family gives infrastructure providers purpose-built ways to connect memory to accelerators, CPUs, and hosts across the rack, turning previously deployed and stranded capacity into a resource that new AI and cloud workloads can use.” Astera said its Leo lines are already being sampled by hyperscalers and offers 62% faster time to first token and 22% more tokens per second. Its latest Leo lines were developed in close collaboration with hyperscalers and hardware partners, including Arm, Intel, AMD, and Samsung. “Our collaboration with Astera Labs around CXL extends that foundation, giving customers greater flexibility to scale memory-intensive AI and cloud workloads and improve infrastructure utilization,” Robert Hormuth, corporate VP for architecture and strategy at AMD, added.