# Arm’s Neoverse CSS N4 raises custom server-chip ceiling to 128 cores per die > Source: > Published: 2026-09-09 13:45:30.733123+00:00 # Arm’s Neoverse CSS N4 raises custom server-chip ceiling to 128 cores per die - Neoverse CSS N4 supports 8 to 128 cores per die, up to 2 MB of L2 cache per core and up to 256 MB of shared L3 cache. [\[1\]](https://www.arm.com/products/cloud-datacenter/neoverse-compute-subsystems/css-n4) - Arm claims up to twice the socket performance, 1.25 times the performance per watt and 1.75 times the memory bandwidth of CSS N3 in a specified 128-core configuration. [\[2\]](https://newsroom.arm.com/news/arm-agi-cpu-neoverse-css-n4-agentic-ai) - The platform targets custom cloud, networking and AI infrastructure silicon rather than finished processors. Arm has not named a CSS N4 customer or disclosed a production schedule. [\[3\]](https://www.tomshardware.com/pc-components/cpus/arm-debuts-next-gen-semi-custom-neoverse-css-n4-ranger-platform-compute-subsystem-packs-up-to-128-cores-per-die-on-tsmc-n3p) - Compared with CSS N2, N4 doubles the maximum core count and L2 cache per core, quadruples the maximum L3 cache and supports newer PCIe and CXL standards. [\[4\]](https://www.arm.com/products/cloud-datacenter/neoverse-compute-subsystems) Arm introduced Neoverse CSS N4 on September 8, 2026, a semi-custom compute platform that lets chip designers build data-center processors with as many as 128 Neoverse N4 cores on one die. The platform also supports up to 256 MB of shared L3 cache, LPDDR6 memory and PCIe Gen 7 connectivity. [\[1\]](https://www.arm.com/products/cloud-datacenter/neoverse-compute-subsystems/css-n4)[\[3\]](https://www.tomshardware.com/pc-components/cpus/arm-debuts-next-gen-semi-custom-neoverse-css-n4-ranger-platform-compute-subsystem-packs-up-to-128-cores-per-die-on-tsmc-n3p) CSS N4 is delivered as a pre-integrated subsystem rather than a finished CPU. Arm combines Neoverse cores with its coherent mesh interconnect, system IP, power and management logic, software and reference designs, allowing partners to customize core count, cache, memory, I/O and accelerator connections. [\[1\]](https://www.arm.com/products/cloud-datacenter/neoverse-compute-subsystems/css-n4)[\[5\]](https://www.arm.com/products/cloud-datacenter/neoverse-compute-subsystems) ## A larger compute and I/O envelope Arm lists CSS N4 configurations from eight to 128 cores per die, with frequencies of up to 3.8 GHz. Each core can be paired with up to 2 MB of private L2 cache, alongside 64 KB instruction and 64 KB data L1 caches. The platform supports up to 256 MB of shared L3 cache per die. [\[1\]](https://www.arm.com/products/cloud-datacenter/neoverse-compute-subsystems/css-n4)[\[3\]](https://www.tomshardware.com/pc-components/cpus/arm-debuts-next-gen-semi-custom-neoverse-css-n4-ranger-platform-compute-subsystem-packs-up-to-128-cores-per-die-on-tsmc-n3p) The subsystem can use DDR5 or LPDDR6 memory and provide as many as 128 PCIe lanes supporting PCIe Gen 6 or Gen 7, as well as CXL 4.0. Tom’s Hardware also reported support for multi-chiplet and multi-socket designs, UCIe-based chip-to-chip links and partner-specific interfaces. [\[3\]](https://www.tomshardware.com/pc-components/cpus/arm-debuts-next-gen-semi-custom-neoverse-css-n4-ranger-platform-compute-subsystem-packs-up-to-128-cores-per-die-on-tsmc-n3p) Arm’s product page describes CSS N4 as an RTL deliverable that can be imported into electronic-design-automation flows. It is not a socketed processor that server buyers can order directly; prospective licensees are directed to Arm representatives and product-support documentation. [\[1\]](https://www.arm.com/products/cloud-datacenter/neoverse-compute-subsystems/css-n4) ## Arm’s performance figures are not independent benchmarks Arm says a reference CSS N4 configuration with 128 cores running at 3 GHz and 2 MB of L2 cache per core delivers twice the socket performance of Neoverse CSS N3, 1.25 times the performance per watt and 1.75 times the memory bandwidth. The announcement does not provide independent benchmark results for production N4 silicon. [\[2\]](https://newsroom.arm.com/news/arm-agi-cpu-neoverse-css-n4-agentic-ai)[\[3\]](https://www.tomshardware.com/pc-components/cpus/arm-debuts-next-gen-semi-custom-neoverse-css-n4-ranger-platform-compute-subsystem-packs-up-to-128-cores-per-die-on-tsmc-n3p) Arm positions the N-series for throughput efficiency and performance per area. Its stated targets include scale-out compute, web services, cloud-native applications, networking, data-plane processing and agentic AI workloads involving CPU-based orchestration and data movement. [\[1\]](https://www.arm.com/products/cloud-datacenter/neoverse-compute-subsystems/css-n4) That places CSS N4 on a different design path from Arm’s Neoverse V-series. Arm describes V-series designs as focused on maximum responsive performance, while N-series designs emphasize throughput and efficiency. [\[1\]](https://www.arm.com/products/cloud-datacenter/neoverse-compute-subsystems/css-n4) ## The step up from CSS N2 Arm lists Neoverse CSS N2 with up to 64 Neoverse N2 cores, 1 MB of private L2 cache per core, 64 MB of shared system-level cache, DDR5 or LPDDR5 memory and PCIe/CXL Gen 5 connectivity. [\[4\]](https://www.arm.com/products/cloud-datacenter/neoverse-compute-subsystems) On those headline specifications, CSS N4 doubles the core ceiling to 128 and the maximum L2 cache per core to 2 MB. Its maximum shared cache is four times larger at 256 MB. The platform also expands the I/O envelope to as many as 128 PCIe lanes and newer PCIe and CXL standards. [\[3\]](https://www.tomshardware.com/pc-components/cpus/arm-debuts-next-gen-semi-custom-neoverse-css-n4-ranger-platform-compute-subsystem-packs-up-to-128-cores-per-die-on-tsmc-n3p)[\[4\]](https://www.arm.com/products/cloud-datacenter/neoverse-compute-subsystems) Arm’s performance comparison uses CSS N3 rather than CSS N2. The company’s claimed 2x socket-performance improvement therefore should not be read as a direct claim that N4 is twice as fast as N2. ## No CSS N4 customer has been announced Arm’s CSS program has previously supported products including Microsoft’s Cobalt 100, Google’s Axion N4A, Alibaba’s Yitian 710 and several networking processors. Those are earlier N-series or Neoverse-based deployments, not announced CSS N4 products. [\[1\]](https://www.arm.com/products/cloud-datacenter/neoverse-compute-subsystems/css-n4) Tom’s Hardware reported that Arm had not identified any CSS N4 partners at launch and that N4-based chips would take time to reach the market because customers must incorporate the subsystem into their own designs. Arm’s public announcement did not provide a general-availability date. [\[3\]](https://www.tomshardware.com/pc-components/cpus/arm-debuts-next-gen-semi-custom-neoverse-css-n4-ranger-platform-compute-subsystem-packs-up-to-128-cores-per-die-on-tsmc-n3p) The process claim also requires qualification. Tom’s Hardware reported TSMC’s N3P process, while ZDNet Korea reported that Arm discussed designs based on TSMC N3/N3P and Samsung SF2/SF2P. Arm’s public CSS N4 product page does not identify one exclusive manufacturing process. [\[3\]](https://www.tomshardware.com/pc-components/cpus/arm-debuts-next-gen-semi-custom-neoverse-css-n4-ranger-platform-compute-subsystem-packs-up-to-128-cores-per-die-on-tsmc-n3p)[\[6\]](https://zdnet.co.kr/view/?no=20260907180808) The competitive comparison is therefore prospective rather than a product benchmark. AMD’s EPYC 9965 is a shipping 192-core x86 server CPU, while CSS N4 is licensable IP that customers must turn into their own silicon. Core count, memory configuration, software support, accelerator connectivity and workload performance will need to be evaluated on actual N4-based products. [\[7\]](https://www.amd.com/content/dam/amd/en/documents/epyc-business-docs/datasheets/amd-epyc-9005-series-processor-datasheet.pdf) ## Companies mentioned ## Further sources The stories that matter, in one email. Free — unsubscribe anytime.