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Apple Neural Engine: Architecture, Programming, and Performance

Researchers reverse-engineered the Apple Neural Engine (ANE), documenting its architecture, programming interface, and performance across A11-A18 and M1-M5 chips. The study reveals a direct user-space route to the ANE, though it remains undocumented and version-fragile, with Core ML as the supported path for shipping software.

read2 min views1 publishedJun 27, 2026
Apple Neural Engine: Architecture, Programming, and Performance
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[Submitted on 21 Jun 2026]


[View PDF](/pdf/2606.22283)

Abstract:The Apple Neural Engine (ANE) is the fixed-function matrix accelerator that has shipped in Apple systems-on-chip since the A11-class iPhone and iPad chips and the M1-class Mac chips, exposed to applications only through the Core ML model framework. This guide reports a reverse-engineered account of the engine, based on direct measurement on Apple silicon and static analysis of the private runtime, compiler, kernel driver, and firmware. It documents the datapath and the roofline that bound the engine's throughput and energy, the dispatch route that reaches it below Core ML, the compiler and on-disk program format, the weight-compression scheme, and the kernel driver, firmware, and command protocol beneath them. The account covers the A11 through A18 and M1 through M5 families, with per-chip target tables and an operation-by-device matrix; the direct measurements are on the M1 and M5. Claims are labeled as measured, decompile-derived, or predicted, and the methodology and open questions are recorded. The direct route is callable from ordinary user space but remains undocumented, unsupported, and version-fragile; it is intended for measurement, research, and on-device work, not for shipping software, where Core ML remains the supported path.

Submission history #

From: Spencer Bryngelson [[view email](/show-email/cf3990d2/2606.22283)]

**[v1]** Sun, 21 Jun 2026 00:17:34 UTC (407 KB)

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