AMD Posts AVX10_V2_AUX ISA Support Patches For GCC Compiler

AMD engineer Dipesh Sharma posted patches for the GNU Compiler Collection to add AVX10_V2_AUX ISA support, which includes dedicated data processing and format conversion instructions for accelerating AI workloads. The AVX10_V2_AUX instruction set adds conversions between standard data types and compressed formats like FP4 and FP6, as well as support for OCP microscaling formats and new rounding modes, as outlined in the ACE v1 specification from the x86 Ecosystem Advisory Group.

AMD Posts AVX10 V2 AUX ISA Support Patches For GCC Compiler Earlier this month Intel compiler engineers posted The AVX10 V2 AUX instruction set adds dedicated data processing and format conversion for helping accelerate AI workloads. AVX10 V2 AUX adds onto AVX10 with instructions for converting standard data types to compressed data formats like FP4 and FP6, support for additional OCP microscaling formats, new rounding modes, and more. All the capabilities are outlined in the Complementing the initial ACE enablement patches for GCC earlier this month from Intel and showing the close collaboration between AMD and Intel engineers around ACE/AVX10 as part of the x86 Ecosystem Advisory Group, AMD engineer Dipesh Sharma posted the latest GNU Compiler Collection patches for plumbing the AVX10 V2 AUX ISA support. The initial GCC compiler patches for the AI Compute Extensions "ACE" https://www.phoronix.com/news/Intel-GCC-ACE-AI-Patches that was born out of the x86 Ecosystem Advisory Group to augment AVX and scalar code with new capabilities for AI/ML workloads. Now as part of that an AMD compiler engineer posted patches over the weekend for AVX10 V2 AUX ISA support.The AVX10 V2 AUX instruction set adds dedicated data processing and format conversion for helping accelerate AI workloads. AVX10 V2 AUX adds onto AVX10 with instructions for converting standard data types to compressed data formats like FP4 and FP6, support for additional OCP microscaling formats, new rounding modes, and more. All the capabilities are outlined in the ACE v1 specification https://x86ecosystem.org/wp-content/uploads/2026/06/ACE v1 Specification public 1 15.pdf .Complementing the initial ACE enablement patches for GCC earlier this month from Intel and showing the close collaboration between AMD and Intel engineers around ACE/AVX10 as part of the x86 Ecosystem Advisory Group, AMD engineer Dipesh Sharma posted the latest GNU Compiler Collection patches for plumbing the AVX10 V2 AUX ISA support. "This series of 7 patches aims to add support for cpuid detection, builtins and intrinsics for AVX10 V2 AUX instructions. AVX10 V2 AUX is a new ISA for x86, supporting converts between FP32-FP8, FP8-FP4, FP8-FP6, and vice-versa." The