# AMD brings UCIe connectivity to Versal adaptive chips > Source: > Published: 2026-08-26 10:36:56+00:00 AMD is adding Universal Chiplet Interconnect Express (UCIe) support to its Versal line of adaptive programmable chips. A modern successor to the Xilinx field-programmable gate arrays following AMD’s [acquisition back in 2022](https://www.amd.com/en/newsroom/press-releases/2022-2-14-amd-completes-acquisition-of-xilinx.html), Versal chips replace monolithic single-use hardware with a chiplet-based reconfigurable system that can be wired up for a specific task or workload ranging from AI acceleration to radio frequency (RF) processing. This latest update sees AMD add UCIe connectivity, allowing the ability to pair them with separate co-packaged chiplets via UCIe, rather than requiring everything built into one monolithic die. The open standard interconnect provides up to multi-terabit-per-second aggregate in-package bandwidth, AMD claims. The chip giant is initially extending support for its RF Versal products with plans to further add system-on-a-chip (SoC) options “as the market matures.” Production chiplets are expected to be available in the fourth quarter of 2027. Kirk Saban, corporate VP for product, software, and solutions in AMD’s embedded business, said in a statement that specialized chiplet designs are driving a new era of innovation in the semiconductor space. “AMD Versal RF Series chiplets are uniquely positioned to be the starting point to harness UCIe connectivity, bringing heterogeneous compute architecture with up to 80 trillion operations per second (TOPS) of digital signal processing (DSP) compute, integrated RF converters and SWAP-C benefits to customers and unlocking the next generation of adaptive RF systems,” the exec added. AMD joined Microsoft, Meta, and Qualcomm in co-developing UCIe specifications in 2022. While its Versal SoCs will feature UCIe 1.1 connectivity, [version 2.0](https://www.synopsys.com/blogs/chip-design/ucie-2-0-setting-the-tone-for-chiplet-interoperability.html) of the specification was released in August 2024, supporting 3D packaging to boost bandwidth density and power efficiency. UCIe is also being used to provide the bridge in [NVLink Fusion](https://www.sdxcentral.com/news/nvidia-launches-nvlink-fusion-to-connect-custom-cpus-and-asics-with-nvidia-hardware/), the Nvidia scale-up-centric backplane allowing non-Nvidia accelerators to intertwine with its hardware. Ayar Labs is among the companies [signed up to NVLink Fusion](https://www.sdxcentral.com/news/ayar-labs-joins-nvlink-fusion-bringing-co-packaged-optics-to-nvidias-ai-infrastructure/) and claimed to be the first vendor to launch an [optical interconnect chiplet built with UCIe](https://www.sdxcentral.com/news/ayar-labs-unveils-worlds-first-ucie-optical-chiplet/) last April.