{"slug": "amd-announces-6th-gen-epyc-server-processors-powered-by-zen-6-microarchitecture", "title": "AMD Announces 6th Gen EPYC Server Processors Powered by \"Zen 6\" Microarchitecture", "summary": "AMD announced the 6th Gen EPYC \"Venice\" server processors powered by the \"Zen 6\" microarchitecture, featuring up to 256 cores and 512 threads with compacted \"Zen 6c\" cores, and up to 1,152 MB of L3 cache on \"Venice-X\" HPC variants. The family includes four product lines—EPYC 9006 (Socket SP7), EPYC 9006 (Socket SP8), EPYC 9006X SP7, and EPYC 9006 LP \"Verano\"—with support for DDR5-8000 RDIMMs, MRDIMMs up to DDR5-12800, and LPDDR5X memory on select models.", "body_md": "AMD today announced the 6th Gen EPYC \"Venice\" server processors powered by the \"Zen 6\" CPU microarchitecture. The family includes a set of four distinct product lines, the EPYC 9006 (Socket SP7) for mainline servers with market leadership in core-counts and performance; the EPYC 9006 (Socket SP8) for enterprises with optimized performance per node; EPYC 9006X SP7 for high performance computing accelerated by larger CPU caches; and the EPYC 9006 LP \"Verano\" processors for AI host nodes powered by LPDDR memory.\n\nThe EPYC 9006 \"Venice\" family offers CPU core counts of up to 96-core/192-thread on chips with \"Zen 6\" cores, and up to 256-core/512-thread on chips with compacted \"Zen 6c\" cores. \"Venice-X\" HPC processors with 3D V-Cache offer up to 1,152 MB of L3 cache per socket. AMD has significantly upgraded the memory sub-system of these processors, giving Socket SP7 a 16-channel DDR5 memory interface with native support for DDR5-8000 RDIMMs, support for MRDIMMs with up to DDR5-12800 speeds. Specific variants also come with 24-channel LPDDR5X interfaces that support field-replaceable SOCAMM2 modules.", "url": "https://wpnews.pro/news/amd-announces-6th-gen-epyc-server-processors-powered-by-zen-6-microarchitecture", "canonical_source": "https://www.techpowerup.com/351000/amd-announces-6th-gen-epyc-server-processors-powered-by-zen-6-microarchitecture", "published_at": "2026-07-23 19:30:01+00:00", "updated_at": "2026-07-23 20:00:50.352844+00:00", "lang": "en", "topics": ["artificial-intelligence", "ai-chips", "ai-infrastructure"], "entities": ["AMD", "EPYC 9006", "Zen 6", "Venice", "SP7", "SP8", "Verano", "SOCAMM2"], "alternates": {"html": "https://wpnews.pro/news/amd-announces-6th-gen-epyc-server-processors-powered-by-zen-6-microarchitecture", "markdown": "https://wpnews.pro/news/amd-announces-6th-gen-epyc-server-processors-powered-by-zen-6-microarchitecture.md", "text": "https://wpnews.pro/news/amd-announces-6th-gen-epyc-server-processors-powered-by-zen-6-microarchitecture.txt", "jsonld": "https://wpnews.pro/news/amd-announces-6th-gen-epyc-server-processors-powered-by-zen-6-microarchitecture.jsonld"}}