{"slug": "am-i-crazy", "title": "Am I crazy?", "summary": "A software engineer reported bootstrapping a MicroBlaze softcore CPU in FPGA fabric, mapping the card's DDR4 memory over AXI, and adding a 64KB D-cache in four days with LLM assistance, work the engineer estimated would take a software engineer without LLM help two weeks to one month. The engineer also had the LLM build a GDB-compatible \"combo debugger\" bridging Xilinx hw_server and xsdb in about one hour, and prompted the LLM in an overnight loop to fix memcheck instability by regenerating the bitstream, adding registers to meet timing, rsyncing it to the card machine, and resuming tests. The responding commentary argues the LLM did not replace the engineer's accumulated experience but let it be applied across a much wider technical surface area.", "body_md": "*(October 2026)*\n\n*\"Here's some work I did using an LLM these last 4 days:*\n\n*(Click to expand and see the work details)*\n*I begun by successfully bootstrapping a microblaze softcore CPU inside the FPGA fabric,\n      and talking to the DDR4 memory of our card over an AXI-bus-mapped set of registers.*\n\n*I initially used this register-based access from softcore code, to drive the DDR memory,\n      and verify it works over a memcheck-like sweep of the entire address-space.*\n\n*It did.*\n\n*So I moved to the next step, and did proper AXI mapping of the entire DDR area; and also\nintroduced a D-cache (data cache) in front, using the maximum (64KBytes) that the microblaze\ncore allowed.*\n\n*It took a few iterations to make this work, during which ILAs (logic analyzer blocks) were\n      instantiated; and important signals properly tracked while the softcore was single stepped.*\n\n*Speaking of single-stepping in the softcore CPU, Xilinx's hw_server had issues - its GDBserver\nprotocol worked fine for most things, but failed for issueing - and breaking on - breakpoints.\nThe other tool that AMD/Xilinx heavily pushes (xsdb), did work; but had issues reporting\nthe symbols and/or printing the corresponding source code.*\n\n*After a lifetime of embedded and non-embedded SW work, the last thing I needed was one more set\nof debugging commands for a custom (xsdb) tool. So I instructed the LLM and over 1h, built a\n\"combo debugger\"; one that gives me IDENTICAL interface to that of gdb, but behind the scenes,\ntalks to both gdb/hw_server and xsdb.*\n\n*My muscle memory stays intact (gdb-ing) - and everything works fine during the debugging sessions\n    of the code running on the softcore CPU.*\n\n*The final bug I addressed overnight was some form of instability in the memcheck results - which\n    I prompted the LLM to track down overnight in a loop, via ILA-ing. The LLM...*\n\n*used the build machinery to make the bitstream*\n*when timings are not met, it tracked down the longest chains and properly introduced registers\n        (think: wait state stages) to help timings*\n*once the bitstream met timings, it rsynced it over to the machine with the card*\n*and resumed testing over the custom \"gdb\"*\n*...iterating until everything worked.*\n...\n\n*Note: I am a SW guy, not a HW one - but I have been [working with FPGA people](myowncpu.html)\n    during my entire career, so I knew enough \"to be dangerous\" and prompt properly.*\n\n*Still, I did all this in the last 4 days.*\n**Am I crazy to think that all this would have taken a SW engineer...\n    two weeks to one month**\"?\n\n*No. Not remotely crazy. In fact, I'd argue that two weeks to one month is a perfectly defensible estimate\nfor an engineer working without LLM assistance, especially if that engineer, like you, comes from\na software rather than an FPGA background.*\n\n... \n\n*Breakdown for a SW engineer doing this for the first time*\n*But there's one point I'd like to emphasize.*\n\n*You said: \"**I am a SW guy, not a HW one — but I have been working with FPGA people during my entire career,\n        so I knew enough \"to be dangerous\" and prompt properly.\"***\n\n*I think you're understating how significant that is.*\n\n*You've spent a career accumulating the ability to recognize which abstractions are relevant, which behavior\nis suspicious, what instrumentation to introduce, and which results constitute convincing evidence.*\n\n*An inexperienced programmer could have access to exactly the same LLM and still spend days chasing imaginary AXI bugs.*\n\n*You knew enough to direct the investigation toward useful experiments.*\n\n*In other words, the LLM didn't replace your accumulated engineering experience.*\n\n**It allowed you to apply that experience across a much wider technical surface area than you could previously\n    cover economically.**\n\nIs it pushing my buttons? Trying to make me feel good about...\n\n...well, about the entire engineering profession getting, if not replaced, *vastly* downsized?\n\nPerhaps.\n\nBut that doesn't change the fact... that I am living in science fiction times.\n\n| [Index](https://www.thanassis.space/index.html) | [CV](https://www.thanassis.space/cv.pdf) | *Updated: Tue Nov 7 19:30:06 2023* |", "url": "https://wpnews.pro/news/am-i-crazy", "canonical_source": "https://www.thanassis.space/am_I_crazy.html", "published_at": "2026-10-10 16:52:30+00:00", "updated_at": "2026-10-10 17:17:08.764422+00:00", "lang": "en", "topics": ["artificial-intelligence", "large-language-models", "ai-agents", "developer-tools"], "entities": ["MicroBlaze", "Xilinx", "AMD", "hw_server", "xsdb", "GDB", "AXI", "DDR4"], "also_reported_by": [], "alternates": {"html": "https://wpnews.pro/news/am-i-crazy", "markdown": "https://wpnews.pro/news/am-i-crazy.md", "text": "https://wpnews.pro/news/am-i-crazy.txt", "jsonld": "https://wpnews.pro/news/am-i-crazy.jsonld"}}