# AI Hardware’s Next Frontier Is Integration > Source: > Published: 2026-08-11 09:25:50+00:00 Artificial intelligence may be driving unprecedented demand for semiconductor performance, but the message from the LID World Summit 2026 was that faster transistors alone will not sustain the next phase of growth. The annual Leti Innovation Days, commonly shortened to LID, brought researchers, technology developers, and industry leaders to Grenoble from June 23 to 25 around a broader challenge: redesigning the entire computing system to move data, deliver power, and manage heat more efficiently. The articles in this series follow that argument from system-level constraints toward industrial implementation. CEA-Leti CEO Sébastien Dauvé began by framing architecture—not raw compute—as AI’s emerging bottleneck. Jean-René Lèquepeys then showed how that architectural problem becomes an energy problem, as data movement, interconnects, power conversion, and cooling consume a growing share of the system budget. The focus next narrows to the technologies needed to respond. François Andrieu explained how emerging and back-end-integrated memories could fill gaps between SRAM, DRAM, and NAND, while Pascal Vivet explained how 3D stacking and chiplet architectures can place those memories closer to processors and widen data paths without ignoring thermal and power-density limits. Eléonore Hardy then traced photonics along the same inward path, from rack-level connections toward co-packaged optics, interposers, and chiplet communication. The series concludes with STMicroelectronics’ Sylvie Gellida, who presented the company’s photonics platform at LID 26, and its effort to ramp silicon photonics on 300-mm wafers. [View All](https://www.eetimes.com/category/sponsored-content/) Together, the articles capture LID 26’s central theme: AI hardware will advance through system co-design, manufacturability, and industrial-scale integration, not through isolated device breakthroughs. [CEA-Leti CEO: AI’s Real Bottleneck Is Architecture](https://www.eetimes.com/cea-leti-ceo-ais-real-bottleneck-is-architecture/) From physical AI and memory-centric architectures to photonics, energy efficiency, and advanced packaging, CEA-Leti’s CEO Sébastien Dauvé outlined the technologies shaping the next phase of AI in an interview with EE Times ahead of the LID World Summit 2026. [The Energy Barrier Reshaping AI Hardware](https://www.eetimes.com/ai-energy-barrier-forces-system-technology-co-optimization/) Researchers at the recent LID 2026 described a shift in how they think about semiconductor roadmaps. The biggest challenges for the near future are delivering electricity efficiently, moving data with less energy, and removing heat from systems that may run continuously at high utilization. **CEA-Leti Looks Beyond SRAM and DRAM as AI Reshapes the Memory Roadmap** In an interview with EE Times, François Andrieu, head of the memory lab at CEA-Leti and a Leti fellow, described more embedded, persistent, and low-energy memories that will meet the growing demands of AI. [CEA-Leti Pushes Stacking Roadmap as AI Runs into Memory and Power Limits](https://www.eetimes.com/cea-leti-pushes-stacking-roadmap-as-ai-runs-into-memory-and-power-limits/) Pascal Vivet, program manager for advanced programs at CEA-Leti, said AI systems need memory placed closer to compute, wider data paths, and earlier co-optimization. [From Co-Packaged Optics to Nanolasers: Photonics Moves Inward](https://www.eetimes.com/from-co-packaged-optics-to-nanolasers-photonics-moves-inward/) CEA-Leti, Scintil Photonics, and NcodiN showed how optical interconnects are moving from data center racks toward co-packaged optics and chiplet-level communication. [AI Data Centers Push Silicon Photonics Toward 300-mm Scale](https://www.eetimes.com/ai-data-centers-push-silicon-photonics-toward-300-mm-scale/) STMicroelectronics and Sicoya discussed how industrializing photonics depends as much on packaging as optical performance.