AI Data Centers Push Silicon Photonics Toward 300-mm Scale

STMicroelectronics is ramping its PIC100 silicon photonics platform on 300-mm wafers to meet the growing demand for optical interconnects in AI data centers, where copper links are reaching limits in bandwidth and power efficiency. The company aims to industrialize silicon photonics for high-volume production, targeting transceiver module makers and PIC design houses that supply hyperscalers.

As AI clusters expand from racks to rows of accelerators, data movement is becoming as critical as compute itself. Data centers need faster links—and that can be provided by photonics. But the optical engines must be producible in volume, packaged compactly, and tested reliably. Moreover, it needs to be integrated close enough to compute to reduce the power and signal losses associated with copper. STMicroelectronics ST bets the next phase of silicon photonics will be shaped by that industrialization challenge. The company is ramping its PIC100 silicon photonics platform on 300-mm wafers while developing the packaging and electrical integration capabilities needed to move optical interconnects closer to processors and switch ASICs. For ST, this is a return to a market that arrived later than expected. According to Sylvie Gellida, general manager of ST’s Optical and RF Foundry Division, the company began working on silicon photonics about a decade ago with an earlier PIC25 platform, which supported at 25-GBaud signaling for 50G-per-lane applications. The technology reached production, but the market was not yet ready. “The killer application wasn’t there,” she told EE Times. “ST put the business activity on hold, but not the R&D, because we believed the application would eventually come. All the planets are now aligned, and we’re on time to address this market.” View All https://www.eetimes.com/category/sponsored-content/ Copper reaches its limits The immediate driver is the move from copper to optics inside AI infrastructure. Copper remains widely used for short electrical links, but as bandwidth rises and clusters expand, it runs into limits in reach, power efficiency, and signal integrity. Gellida said AI data centers need more routing capability in the rack and more bandwidth in less physical space between elements of the system. Copper increasingly constrains both. Optical links offer better reach, lower loss, and better signal integrity while supporting more compact optical engines that convert electrical signals into optical signals and back again. Pluggable optical transceivers remain the largest near-term market, Gellida said, particularly for scale-out networks. Near-packaged optics NPO will serve as an intermediate step by moving optics closer to the ASIC, while co-packaged optics CPO comes later as the ecosystem solves reliability and serviceability challenges. Packaging is central to that roadmap. ST is developing through-silicon via, or TSV, options for PIC100 and its BiCMOS platform. Gellida said TSVs can reduce interconnection loss between the photonic IC, substrate, and electronic ICs, improving compactness, signal integrity, and performance. But she added that moving optics closer to compute also requires thermal design, fiber attach, and new serviceability models. ST’s PIC100 platform is its current silicon photonics technology for optical interconnects. The name refers to photonic integrated circuits PICs , which supports 100-GBaud signaling for 200G-per-lane applications. Gellida said ST’s differentiation is not simply that PIC100 can support 200G per lane. Other platforms can also reach that class of performance. The distinction, she said, is that ST is ramping the technology on 300-mm wafers and demonstrating yields comparable to CMOS manufacturing https://www.embedded.com/equal1-reaches-quantum-milestone-with-cmos-process-validation-for-scalable-silicon-spin-qubits/ . “Today we’re supplying silicon photonics wafers in Crolles, France, on 300-mm wafers,” she said. “For the volumes required by AI data centers and AI factories, 300-mm manufacturing brings together tools, accuracy, volume, and yield.” ST’s direct customers are not usually hyperscalers themselves. They are transceiver module makers and PIC design houses that use ST’s silicon photonics and BiCMOS technologies to build optical engines, transceivers, and modules. Those modules then feed into the hyperscaler ecosystem. The company’s ambition is broader than supplying wafers. ST is combining silicon photonics with BiCMOS for laser drivers and electronic ICs, STM32 microcontrollers for module control, and advanced packaging options including TSVs, bumping, packaging, and testing support. Gellida described this as a move toward becoming a “one-stop shop” for optical interconnect building blocks. Sicoya ’ s 1.6T proof point Sicoya, a Berlin-based silicon photonics company, offers an early example of what that platform strategy can enable. At OFC in March, Sicoya demonstrated a PIC100-based OSFP module targeting 1.6T DR8 operation. In practical terms, that means eight lanes running at 200G per lane. Hanjo Rhee, CTO and managing director at Sicoya, said the module is aimed at scale-out networks and the continuation of pluggable architectures used in cloud data centers. The demonstration used both photonic and electronic ICs from ST. Sicoya designed the transceiver PIC, including both transmitter and receiver functions, and its own transimpedance amplifiers. The TIA was die-stacked on top of the PIC, creating extremely short connections between the photodiodes and the electronic amplifier. “The demo proved that these more complex photonic products for these pluggables are possible and that they are possible with ST’s platform,” he told EE Times. The significance is partly technical and partly industrial. Sicoya previously worked with smaller foundry partners and even built its own modules, but foundry capacity became a limiting factor. The company has since shifted toward chip-level products, including PICs, electronic ICs, and die-stacked combinations. Rhee said the market is eager for another high-volume silicon photonics platform. Tower Semiconductor has significant photonics capacity, he said, but much of it is based on 200-mm manufacturing and is heavily booked. TSMC also has offerings, but access can be difficult. A 300-mm ST platform gives companies such as Sicoya a volume-capable foundry partner. The Sicoya demo also shows why silicon photonics industrialization is not only about the optical device. Much of the value lies in the way the PIC, EIC, package, and control functions are brought together. Rhee said Sicoya deliberately chose die stacking. It had previously used monolithic integration, where electronics and photonics sit on the same chip. That approach offers very short RF paths and good signal integrity, but it also creates development-cycle and foundry-volume constraints. “Die stacking is a better choice,” he said, “It brings electronics and photonics close together. Plus, it’s on a foundry platform that can scale and the technologies are updated more quickly.” Short signal paths can reduce parasitics and improve performance. They can also simplify the module maker’s job. If control loops run internally between the electronic IC and the photonic IC, the module manufacturer doesn’t have to manage every control feature through an external microcontroller. Rhee gave the example of a variable optical attenuator integrated into the waveguides leading to the photodiode. The attenuator can be controlled by the TIA sitting on top of the PIC, limiting the optical power seen by the photodiode. That can improve receiver sensitivity and bit-error-rate behavior by preventing excess optical intensity from overloading the receiver path. “That’s a feature you can implement in a die stack, but you cannot implement in a larger package or chipset in an efficient way,” he said. As optics move from pluggables toward NPO and CPO, those packaging issues become even more important. Rhee said moving closer to the switch ASIC or GPU should allow the industry to get rid of the DSP in some cases, because shorter electrical paths reduce the need for retiming. But it also makes footprint, connector design, and high-volume assembly harder. One major challenge is how to attach optics when the optical engine is soldered to the main board. A conventional optical connector cannot simply be glued before reflow soldering, because it may not survive the process. Rhee said large packaging companies are now working on detachable optical connectors and other approaches for high-volume NPO and CPO assembly. “You can do this in smaller volumes for sure,” he said. “But to do this large scale is very hard.” For ST, one big priority is proving PIC100 can scale like a semiconductor platform. For Sicoya, it’s showing that dense packaging and die stacking can turn that platform into usable optical engines. AI data centers may be driving the need for photonics. But the next phase of the market will be won by companies that can industrialize it. See also: Paving the Way for Integrated Photonic Chips https://www.eetimes.com/paving-the-way-for-integrated-photonic-chips/ AI Demand Reshapes Optical Connectivity and Photonics Roadmaps https://www.eetimes.com/ai-demand-reshapes-optical-connectivity-and-photonics-roadmaps/