FPGA — Web Pulse coverage

80386 Memory Pipeline :: https://wpnews.pro/news/80386-memory-pipeline
UART in Verilog with Fractional Clock Dividers :: https://wpnews.pro/news/uart-in-verilog-with-fractional-clock-dividers
Building GBATang part 2 - memory system and others :: https://wpnews.pro/news/building-gbatang-part-2-memory-system-and-others
Adding a Softcore to SNESTang - part 2 :: https://wpnews.pro/news/adding-a-softcore-to-snestang-part-2