{"entity": "FPGA", "url": "https://wpnews.pro/entity/FPGA", "count": 4, "articles": [{"slug": "80386-memory-pipeline", "title": "80386 Memory Pipeline", "url": "https://wpnews.pro/news/80386-memory-pipeline", "published_at": "2026-04-14 00:00:00+00:00"}, {"slug": "uart-in-verilog-with-fractional-clock-dividers", "title": "UART in Verilog with Fractional Clock Dividers", "url": "https://wpnews.pro/news/uart-in-verilog-with-fractional-clock-dividers", "published_at": "2025-02-25 00:00:00+00:00"}, {"slug": "building-gbatang-part-2-memory-system-and-others", "title": "Building GBATang part 2 - memory system and others", "url": "https://wpnews.pro/news/building-gbatang-part-2-memory-system-and-others", "published_at": "2024-09-28 00:00:00+00:00"}, {"slug": "adding-a-softcore-to-snestang-part-2", "title": "Adding a Softcore to SNESTang - part 2", "url": "https://wpnews.pro/news/adding-a-softcore-to-snestang-part-2", "published_at": "2024-02-07 00:00:00+00:00"}]}